LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 187

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
12.3.8 GPIO masked interrupt status register
12.3.9 GPIO interrupt clear register
Table 179. GPIOnRIS register (GPIO0RIS, address 0x5000 8014 to GPIO3RIS, address 0x5003
Bits read HIGH in the GPIOnMIS register reflect the status of the input lines triggering an
interrupt. Bits read as LOW indicate that either no interrupt on the corresponding input
pins has been generated or that the interrupt is masked. GPIOMIS is the state of the
interrupt after masking. The register is read-only.
Table 180. GPIOnMIS register (GPIO0MIS, address 0x5000 8018 to GPIO3MIS, address
This register allows software to clear edge detection for port bits that are identified as
edge-sensitive in the Interrupt Sense register. This register has no effect on port bits
identified as level-sensitive.
Table 181. GPIOnIC register (GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003
Bit
11:0
31:12
Bit
11:0
31:12
Bit
11:0
31:12
Symbol Description
RAWST Raw interrupt status (x = 0 to 11).
-
Symbol Description
MASK
-
Symbol
CLR
-
8014) bit description
0x5003 8018) bit description
801C) bit description
All information provided in this document is subject to legal disclaimers.
Selects interrupt on pin x to be masked (x = 0 to 11).
0 = No interrupt or interrupt masked on pin PIOn_x.
1 = Interrupt on PIOn_x.
Reserved
0 = No interrupt on pin PIOn_x.
1 = Interrupt requirements met on PIOn_x.
Reserved
Description
Selects interrupt on pin x to be cleared (x = 0 to 11). Clears
the interrupt edge detection logic. This register is write-only.
Remark: The synchronizer between the GPIO and the
NVIC blocks causes a delay of 2 clocks. It is recommended
to add two NOPs after the clear of the interrupt edge
detection logic before the exit of the interrupt service
routine.
0 = No effect.
1 = Clears edge detection logic for pin PIOn_x.
Reserved
Rev. 12 — 24 September 2012
Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
0x00
-
Reset
value
0x00
-
Reset
value
0x00
-
Access
W
-
Access
R
-
Access
R
-
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