LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 529

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)
12.1
12.2
12.2.1
12.3
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
Chapter 13: LPC111x/LPC11Cxx UART
13.1
13.2
13.3
13.4
13.5
13.5.1
13.5.2
13.5.3
13.5.4
13.5.5
13.5.6
13.5.7
13.5.8
13.5.8.1
13.5.8.1.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.5.8.1.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
13.5.9
13.5.10
13.5.11
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
14.1
14.2
14.3
14.4
14.5
14.6
14.6.1
14.6.2
14.6.3
14.6.4
14.6.5
UM10398
User manual
How to read this chapter . . . . . . . . . . . . . . . . 183
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Register description . . . . . . . . . . . . . . . . . . . 184
How to read this chapter . . . . . . . . . . . . . . . . 190
Basic configuration . . . . . . . . . . . . . . . . . . . . 190
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 191
Register description . . . . . . . . . . . . . . . . . . . 191
How to read this chapter . . . . . . . . . . . . . . . . 217
Basic configuration . . . . . . . . . . . . . . . . . . . . 217
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
General description . . . . . . . . . . . . . . . . . . . . 217
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 218
Register description . . . . . . . . . . . . . . . . . . . 219
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
GPIO data register . . . . . . . . . . . . . . . . . . . . 184
GPIO data direction register . . . . . . . . . . . . . 185
GPIO interrupt sense register . . . . . . . . . . . . 185
GPIO interrupt both edges sense register . . 186
GPIO interrupt event register . . . . . . . . . . . . 186
UART Receiver Buffer Register (U0RBR -
0x4000 8000, when DLAB = 0, Read Only) . 193
UART Transmitter Holding Register (U0THR -
0x4000 8000 when DLAB = 0, Write Only). . 193
UART Divisor Latch LSB and MSB Registers
(U0DLL - 0x4000 8000 and U0DLM -
0x4000 8004, when DLAB = 1). . . . . . . . . . . 193
UART Interrupt Enable Register (U0IER -
0x4000 8004, when DLAB = 0). . . . . . . . . . . 194
UART Interrupt Identification Register (U0IIR -
0x4004 8008, Read Only). . . . . . . . . . . . . . . 195
UART FIFO Control Register (U0FCR -
0x4000 8008, Write Only) . . . . . . . . . . . . . . . 197
UART Line Control Register (U0LCR -
0x4000 800C) . . . . . . . . . . . . . . . . . . . . . . . . 198
UART Modem Control Register . . . . . . . . . . 199
Auto-flow control . . . . . . . . . . . . . . . . . . . . . . 200
UART Line Status Register (U0LSR -
0x4000 8014, Read Only). . . . . . . . . . . . . . . 202
UART Modem Status Register . . . . . . . . . . . 204
UART Scratch Pad Register (U0SCR -
0x4000 801C) . . . . . . . . . . . . . . . . . . . . . . . . 204
SPI/SSP Control Register 0 . . . . . . . . . . . . . 219
SPI/SSP0 Control Register 1 . . . . . . . . . . . . 220
SPI/SSP Data Register . . . . . . . . . . . . . . . . 221
SPI/SSP Status Register . . . . . . . . . . . . . . . 222
SPI/SSP Clock Prescale Register . . . . . . . . 222
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
12.3.6
12.3.7
12.3.8
12.3.9
12.4
12.4.1
13.5.12
13.5.13
13.5.14
13.5.15
13.5.15.1 Baud rate calculation . . . . . . . . . . . . . . . . . . 209
13.5.15.1.1 Example 1: UART_PCLK = 14.7456 MHz, BR =
13.5.15.1.2 Example 2: UART_PCLK = 12 MHz, BR =
13.5.16
13.5.17
13.5.18
13.5.19
13.5.20
13.6
14.6.6
14.6.7
14.6.8
14.6.9
14.7
14.7.1
14.7.2
14.7.2.1
14.7.2.2
Functional description . . . . . . . . . . . . . . . . . 188
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Functional description . . . . . . . . . . . . . . . . . 224
GPIO interrupt mask register . . . . . . . . . . . . 186
GPIO raw interrupt status register . . . . . . . . 186
GPIO masked interrupt status register. . . . . 187
GPIO interrupt clear register . . . . . . . . . . . . 187
Write/read data operation. . . . . . . . . . . . . . . 188
Write operation. . . . . . . . . . . . . . . . . . . . . . . . 188
Read operation . . . . . . . . . . . . . . . . . . . . . . . 189
UART Auto-baud Control Register (U0ACR -
0x4000 8020) . . . . . . . . . . . . . . . . . . . . . . . . 205
Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 206
UART Fractional Divider Register (U0FDR -
0x4000 8028) . . . . . . . . . . . . . . . . . . . . . . . . 208
9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
115200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
UART Transmit Enable Register (U0TER -
0x4000 8030) . . . . . . . . . . . . . . . . . . . . . . . . . 211
UART RS485 Control register (U0RS485CTRL -
0x4000 804C) . . . . . . . . . . . . . . . . . . . . . . . 212
UART RS485 Address Match register
(U0RS485ADRMATCH - 0x4000 8050) . . . . 213
UART1 RS485 Delay value register
(U0RS485DLY - 0x4000 8054) . . . . . . . . . . 213
RS-485/EIA-485 modes of operation . . . . . . 213
RS-485/EIA-485 Normal Multidrop Mode
(NMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
RS-485/EIA-485 Auto Address Detection (AAD)
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
RS-485/EIA-485 Auto Direction Control. . . . . 214
RS485/EIA-485 driver delay time. . . . . . . . . . 215
RS485/EIA-485 output inversion . . . . . . . . . . 215
SPI/SSP Interrupt Mask Set/Clear Register
SPI/SSP Raw Interrupt Status Register . . . 223
SPI/SSP Masked Interrupt Status Register . 223
SPI/SSP Interrupt Clear Register . . . . . . . . 224
Texas Instruments synchronous serial frame
format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
SPI frame format . . . . . . . . . . . . . . . . . . . . . 225
Clock Polarity (CPOL) and Phase (CPHA)
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
SPI format with CPOL=0,CPHA=0. . . . . . . . 226
Chapter 29: Supplementary information
UM10398
© NXP B.V. 2012. All rights reserved.
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