LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 393

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
23.7 Register description
UM10398
User manual
23.7.1 Watchdog Mode register (WDMOD - 0x4000 0000)
The Watchdog contains four registers as shown in
Table 350. Register overview: Watchdog timer (base address 0x4000 4000)
[1]
The WDMOD register controls the operation of the Watchdog through the combination of
WDEN and RESET bits. Note that a watchdog feed must be performed before any
changes to the WDMOD register take effect.
Table 351. Watchdog Mode register (WDMOD - address 0x4000 4000) bit description
Once the WDEN and/or WDRESET bits are set, they can not be cleared by software. Both
flags are cleared by a reset or a Watchdog timer underflow.
WDTOF The Watchdog time-out flag is set when the Watchdog times out. This flag is
cleared by software or a POR or Brown-Out-Detect reset.
Name
WDMOD
WDTC
WDFEED
WDTV
Bit
0
1
2
3
7:4
31:8 -
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Symbol
WDEN
WDRESET WDRESET Watchdog reset enable bit (Set Only). When 1,
WDTOF
WDINT
-
Access Address
R/W
R/W
WO
RO
All information provided in this document is subject to legal disclaimers.
Description
WDEN Watchdog enable bit (Set Only). When 1, the
watchdog timer is running.
Remark: Setting this bit to one also locks the watchdog
clock source. Once the watchdog timer is enabled, the
watchdog timer clock source cannot be changed. If the
watchdog timer is needed in Deep-sleep mode, the
watchdog clock source must be changed to the watchdog
oscillator before setting this bit to one. The clock source
lock feature is not available on all parts, see
a watchdog time-out will cause a chip reset.
WDTOF Watchdog time-out flag. Set when the watchdog
timer times out, cleared by software.
WDINT Watchdog interrupt flag (Read Only, not clearable
by software).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
reserved
Rev. 12 — 24 September 2012
offset
0x000
0x004
0x008
0x00C
Chapter 23: LPC111x/LPC11Cxx WatchDog Timer (WDT)
Description
Watchdog mode register. This register contains the
basic mode and status of the Watchdog Timer.
Watchdog timer constant register. This register
determines the time-out value.
Watchdog feed sequence register. Writing 0xAA
followed by 0x55 to this register reloads the
Watchdog timer with the value contained in WDTC.
Watchdog timer value register. This register reads
out the current value of the Watchdog timer.
Table 350
Section
below.
23.1).
UM10398
© NXP B.V. 2012. All rights reserved.
Reset Value
0
0
0 (Only after
POR and BOD
reset)
0
NA
-
393 of 538
Reset
Value
0
0xFF
NA
0xFF
[1]