LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 283

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
16.6.1.4 CAN bit timing register
Table 248. CAN bit timing register (CANBT, address 0x4005 000C) bit description
[1]
For example, with a LPC11Cx system clock set to of 8 MHz, the reset value of 0x2301
configures the C_CAN for a bit rate of 500 kBit/s.
The registers are only writable if a configuration change is enabled in CANCTRL and the
controller is initialized by software (bits CCE and INIT in the CAN Control Register are
set).
For details on bit timing, see
revision 1.2.
Baud rate prescaler
The bit time quanta t
t
(f
Time segments 1 and 2
Time segments TSEG1 and TSEG2 determine the number of time quanta per bit time
and the location of the sample point:
t
Synchronization jump width
To compensate for phase shifts between clock oscillators of different bus controllers, any
bus controller must re-synchronize on any relevant signal edge of the current
transmission. The synchronization jump width t
cycles a certain bit period may be shortened or lengthened by one re-synchronization:
t
Bit
5:0
7:6
11:8
14:12
31:15
q
TSEG1/2
SJW
sys
= BRP / f
Hardware interprets the value programmed into these bits as the bit value  1.
is the LPC11Cx system clock to the C_CAN block).
= t
q
Symbol
BRP
SJW
TSEG1
TSEG2
-
= t
 (SJW + 1)
q
sys
 (TSEG1/2 + 1)
All information provided in this document is subject to legal disclaimers.
Description
Baud rate prescaler
The value by which the oscillator frequency is divided for
generating the bit time quanta. The bit time is built up from
a multiple of this quanta. Valid values for the Baud Rate
Prescaler are 0 to 63.
(Re)synchronization jump width
Valid programmed values are 0 to 3.
Time segment before the sample point
Valid values are 1 to 15.
Time segment after the sample point
Valid values are 0 to 7.
Reserved
q
Rev. 12 — 24 September 2012
are determined by the BRP value:
Section 16.7.5
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
[1]
[1]
[1]
and the Bosch C_CAN user’s manual,
SJW
[1]
defines the maximum number of clock
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
000001
00
0011
010
-
283 of 538
Access
R/W
R/W
R/W
R/W
-