LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 242

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
15.8 I
UM10398
User manual
2
C operating modes
15.7.10 I
15.8.1 Master Transmitter mode
Table 229. I
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to ‘1’ will cause an automatic compare on the corresponding bit of the
received address when it is compared to the ADDRn register associated with that mask
register. In other words, bits in an ADDRn register which are masked are not taken into
account in determining an address match.
On reset, all mask register bits are cleared to ‘0’.
The mask register has no effect on comparison to the General Call address (“0000000”).
Bits(31:8) and bit(0) of the mask registers are unused and should not be written to. These
bits will always read back as zeros.
When an address-match interrupt occurs, the processor will have to read the data register
(DAT) to determine what the received address was that actually caused the match.
Table 230. I
In a given application, the I
mode, the I
address. If one of these addresses is detected, an interrupt is requested. If the processor
wishes to become the bus master, the hardware waits until the bus is free before the
master mode is entered so that a possible slave operation is not interrupted. If bus
arbitration is lost in the master mode, the I
immediately and can detect its own slave address in the same serial transfer.
In this mode data is transmitted from master to slave. Before the master transmitter mode
can be entered, the CONSET register must be initialized as shown in
must be set to 1 to enable the I
acknowledge any address when another device is master of the bus, so it can not enter
slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the
SIC bit in the CONCLR register. THe STA bit should be cleared after writing the slave
address.
Bit
7:0
31:8 -
Bit
0
7:1
31:8
2
C Mask registers (I2C0MASK[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3C])
Symbol
Data
Symbol
-
MASK
-
description
2
2
2
C hardware looks for any one of its four slave addresses and the General Call
C Data buffer register (I2C0DATA_BUFFER - 0x4000 002C) bit description
C Mask registers (I2C0MASK[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3C]) bit
All information provided in this document is subject to legal disclaimers.
Description
This register holds contents of the 8 MSBs of the DAT shift
register.
Reserved. The value read from a reserved bit is not defined.
Description
Reserved. User software should not write ones to reserved
bits. This bit reads always back as 0.
Mask bits.
Reserved. The value read from reserved bits is undefined.
Rev. 12 — 24 September 2012
2
C block may operate as a master, a slave, or both. In the slave
2
C function. If the AA bit is 0, the I
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
2
C block switches to the slave mode
2
C interface will not
Table
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0
0x00
0
0
Reset value
0
231. I2EN
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