LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 279

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
16.6.1.1 CAN control register
16.6.1 CAN protocol registers
The reset value 0x0001 of the CANCTRL register enables initialization by software (INIT =
1). The C_CAN does not influence the CAN bus until the CPU resets the INIT bit to 0.
Table 245. CAN control registers (CANCNTL, address 0x4005 0000) bit description
Bit
0
1
2
3
4
5
6
7
31:8
Symbol Value
INIT
IE
SIE
EIE
-
DAR
CCE
TEST
-
All information provided in this document is subject to legal disclaimers.
0
1
0
1
0
1
0
1
-
0
1
0
1
0
1
Rev. 12 — 24 September 2012
Description
Initialization
Normal operation.
Initialization is started. On reset, software
needs to initialize the CAN controller.
Module interrupt enable
Disable CAN interrupts. The interrupt line is
always HIGH.
Enable CAN interrupts. The interrupt line is set
to LOW and remains LOW until all pending
interrupts are cleared.
Status change interrupt enable
Disable status change interrupts. No status
change interrupt will be generated.
Enable status change interrupts. A status
change interrupt will be generated when a
message transfer is successfully completed or
a CAN bus error is detected.
Error interrupt enable
Disable error interrupt. No error status interrupt
will be generated.
Enable error interrupt. A change in the bits
BOFF or EWARN in the CANSTAT registers
will generate an interrupt.
reserved
Disable automatic retransmission
Automatic retransmission of disturbed
messages enabled.
Automatic retransmission disabled.
Configuration change enable
The CPU has no write access to the bit timing
register.
The CPU has write access to the CANBT
register while the INIT bit is one.
Test mode enable
Normal operation.
Test mode.
reserved
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
Reset
value
1
0
0
0
0
0
0
0
-
UM10398
© NXP B.V. 2012. All rights reserved.
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