LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 247

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
15.9.2 Address Registers, ADDR0 to ADDR3
15.9.3 Address mask registers, MASK0 to MASK3
15.9.4 Comparator
15.9.5 Shift register, DAT
15.9.6 Arbitration and synchronization logic
These registers may be loaded with the 7-bit slave address (7 most significant bits) to
which the I
LSB (GC) is used to enable General Call address (0x00) recognition. When multiple slave
addresses are enabled, the actual address received may be read from the DAT register at
the state where the own slave address has been received.
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to ‘1’ will cause an automatic compare on the corresponding bit of the
received address when it is compared to the ADDRn register associated with that mask
register. In other words, bits in an ADDRn register which are masked are not taken into
account in determining an address match.
When an address-match interrupt occurs, the processor will have to read the data register
(DAT) to determine what the received address was that actually caused the match.
The comparator compares the received 7-bit slave address with its own slave address (7
most significant bits in ADR). It also compares the first received 8-bit byte with the
General Call address (0x00). If an equality is found, the appropriate status bits are set and
an interrupt is requested.
This 8-bit register contains a byte of serial data to be transmitted or a byte which has just
been received. Data in DAT is always shifted from right to left; the first bit to be transmitted
is the MSB (bit 7) and, after a byte has been received, the first bit of received data is
located at the MSB of DAT. While data is being shifted out, data on the bus is
simultaneously being shifted in; DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master transmitter to slave
receiver is made with the correct data in DAT.
In the master transmitter mode, the arbitration logic checks that every transmitted logic 1
actually appears as a logic 1 on the I
1 and pulls the SDA line low, arbitration is lost, and the I
from master transmitter to slave receiver. The I
pulses (on SCL) until transmission of the current serial byte is complete.
Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode
can only occur while the I
Arbitration is lost when another device on the bus pulls this signal low. Since this can
occur only at the end of a serial byte, the I
Figure 51
shows the arbitration procedure.
2
C block will respond when programmed as a slave transmitter or receiver. The
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
2
C block is returning a “not acknowledge: (logic 1) to the bus.
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
2
C-bus. If another device on the bus overrules a logic
2
C block generates no further clock pulses.
2
C block will continue to output clock
2
C block immediately changes
UM10398
© NXP B.V. 2012. All rights reserved.
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