LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 36

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.5.29 Start logic edge control register 0
3.5.30 Start logic signal enable register 0
Table 35.
Note: If the NMISRC register is used to select an interrupt as the source of Non-Maskable
interrupts, and the selected interrupt is enabled, one interrupt request can result in both a
Non-Maskable and a normal interrupt. Avoid this situation by disabling the normal
interrupt in the NVIC, as described in
The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11)
and 1 (PIO1_0). This register selects a falling or rising edge on the corresponding PIO
input to produce a falling or rising clock edge, respectively, for the start logic (see
Section
Every bit in the STARTAPRP0 register controls one port input and is connected to one
wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt
0, bit 1 to interrupt 1, etc. (see
Remark: Each interrupt connected to a start logic input must be enabled in the NVIC if the
corresponding PIO pin is used to wake up the chip from Deep-sleep mode.
Table 36.
This STARTERP0 register enables or disables the start signal bits in the start logic. The
bit assignment is identical to
Bit
4:0
30:5
31
Bit
11:0
12
31:13 -
Symbol Description
IRQNO
-
NMIEN
Symbol
APRPIO0_n
3.10.2).
APRPIO1_0
NMI source selection register (NMISRC, address 0x4004 8174) bit description
Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit
description
All information provided in this document is subject to legal disclaimers.
The IRQ number of the interrupt that acts as the Non-Maskable Interrupt
(NMI) if bit 31 in this register is 1. See
sources and their IRQ numbers.
Reserved
Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source
selected by bits 4:0.
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
Description
Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0
0 = Falling edge
1 = Rising edge
Edge select for start logic input PIO1_0
0 = Falling edge
1 = Rising edge
Reserved. Do not write a 1 to reserved bits in this register.
Table
Table
36.
54), up to a total of 13 interrupts.
Section
28.6.2.
Table 54
for the list of interrupt
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
0x0
0x0
0x0
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0
-
0
Reset
value