LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 44

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
3.9 Power management
UM10398
User manual
3.9.1.1 Power configuration in Active mode
3.9.2.1 Power configuration in Sleep mode
3.9.1 Active mode
3.9.2 Sleep mode
The LPC111x/LPC11Cxx support a variety of power control features. In Active mode,
when the chip is running, power and clocks to selected peripherals can be optimized for
power consumption. In addition, there are three special modes of processor power
reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode.
Remark: The Debug mode is not supported in Sleep, Deep-sleep, or Deep power-down
modes.
In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock,
and peripherals are clocked by the system clock or a dedicated peripheral clock.
The chip is in Active mode after reset and the default power configuration is determined
by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power
configuration can be changed during run time.
Power consumption in Active mode is determined by the following configuration choices:
In Sleep mode, the system clock to the ARM Cortex-M0 core is stopped, and execution of
instructions is suspended until either a reset or an enabled interrupt occurs.
Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register, continue
operation during Sleep mode and may generate interrupts to cause the processor to
resume execution. Sleep mode eliminates dynamic power used by the processor itself,
memory systems and their related controllers, and internal buses. The processor state
and registers, peripheral registers, and internal SRAM values are maintained, and the
logic levels of the pins remain static.
Power consumption in Sleep mode is configured by the same settings as in Active mode:
•
•
•
•
•
•
The SYSAHBCLKCTRL register controls which memories and peripherals are
running
The power to various analog blocks (PLL, oscillators, the ADC, the BOD circuit, and
the flash block) can be controlled at any time individually through the PDRUNCFG
register
The clock source for the system clock can be selected from the IRC (default), the
system oscillator, or the watchdog oscillator (see
The system clock frequency can be selected by the SYSPLLCTRL
SYSAHBCLKDIV register
Selected peripherals (UART, SPI0/1, WDT) use individual peripheral clocks with their
own clock dividers. The peripheral clocks can be shut down through the
corresponding clock divider registers
The clock remains running.
(Table
(Table
All information provided in this document is subject to legal disclaimers.
21).
43).
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
(Table
20).
(Table 22
to
Figure 8
Table
24).
and related registers).
UM10398
(Table
© NXP B.V. 2012. All rights reserved.
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