LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 254

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
15.10.2 Master Receiver mode
In the master receiver mode, a number of data bytes are received from a slave transmitter
(see
START condition has been transmitted, the interrupt service routine must load DAT with
the 7-bit slave address and the data direction bit (SLA+R). The SI bit in CON must then be
cleared before the serial transfer can continue.
When the slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in STAT are possible. These are 0x40, 0x48, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The
appropriate action to be taken for each of these status codes is detailed in
a Repeated START condition (state 0x10), the I
transmitter mode by loading DAT with SLA+W.
Figure
54). The transfer is initialized as in the master transmitter mode. When the
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
2
C block may switch to the master
UM10398
© NXP B.V. 2012. All rights reserved.
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