LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 193

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
13.5.1 UART Receiver Buffer Register (U0RBR - 0x4000 8000, when
13.5.2 UART Transmitter Holding Register (U0THR - 0x4000 8000 when
13.5.3 UART Divisor Latch LSB and MSB Registers (U0DLL - 0x4000 8000
DLAB = 0, Read Only)
The U0RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0RBR. The U0RBR is always Read Only.
Since PE, FE and BI bits (see
RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach
for fetching the valid pair of received byte and its status bits is first to read the content of
the U0LSR register, and then to read a byte from the U0RBR.
Table 184. UART Receiver Buffer Register (U0RBR - address 0x4000 8000 when DLAB = 0,
DLAB = 0, Write Only)
The U0THR is the top byte of the UART TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0THR. The U0THR is always Write Only.
Table 185. UART Transmitter Holding Register (U0THR - address 0x4000 8000 when
and U0DLM - 0x4000 8004, when DLAB = 1)
The UART Divisor Latch is part of the UART Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the UART_PCLK clock in order to
produce the baud rate clock, which must be 16x the desired baud rate. The U0DLL and
U0DLM registers together form a 16-bit divisor where U0DLL contains the lower 8 bits of
the divisor and U0DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated
like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit
(DLAB) in U0LCR must be one in order to access the UART Divisor Latches. Details on
how to select the right value for U0DLL and U0DLM can be found in
Bit
7:0
31:8 -
Bit
7:0
31:8 -
Symbol
RBR
Symbol
THR
Read Only) bit description
DLAB = 0, Write Only) bit description
All information provided in this document is subject to legal disclaimers.
Description
The UART Receiver Buffer Register contains the oldest received
byte in the UART RX FIFO.
Reserved
Description
Writing to the UART Transmit Holding Register causes the data
to be stored in the UART transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.
Reserved
Rev. 12 — 24 September 2012
Table
195) correspond to the byte sitting on the top of the
Chapter 13: LPC111x/LPC11Cxx UART
Section
UM10398
© NXP B.V. 2012. All rights reserved.
Reset Value
undefined
-
Reset Value
NA
-
13.5.15.
193 of 538