LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 401

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
25.5 Register description
Table 362. Register overview: ADC (base address 0x4001 C000)
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UM10398
User manual
Name
AD0CR
AD0GDR
-
AD0INTEN R/W
AD0DR0
AD0DR1
AD0DR2
AD0DR3
AD0DR4
AD0DR5
AD0DR6
AD0DR7
AD0STAT
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Access Address
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
Table 361. ADC pin description
The ADC function must be selected via the IOCON registers in order to get accurate
voltage readings on the monitored pin. For a pin hosting an ADC input, it is not possible to
have a have a digital function selected and yet get valid ADC readings. An inside circuit
disconnects ADC hardware from the associated pin whenever a digital function is selected
on that pin.
Pin
AD[7:0]
V
The ADC contains registers organized as shown in
DD
Description
A/D Control Register. The AD0CR register must be written to select the
operating mode before A/D conversion can occur.
A/D Global Data Register. Contains the result of the most recent A/D
conversion.
Reserved.
A/D Interrupt Enable Register. This register contains enable bits that allow
the DONE flag of each A/D channel to be included or excluded from
contributing to the generation of an A/D interrupt.
A/D Channel 0 Data Register. This register contains the result of the most
recent conversion completed on channel 0
A/D Channel 1 Data Register. This register contains the result of the most
recent conversion completed on channel 1.
A/D Channel 2 Data Register. This register contains the result of the most
recent conversion completed on channel 2.
A/D Channel 3 Data Register. This register contains the result of the most
recent conversion completed on channel 3.
A/D Channel 4 Data Register. This register contains the result of the most
recent conversion completed on channel 4.
A/D Channel 5 Data Register. This register contains the result of the most
recent conversion completed on channel 5.
A/D Channel 6 Data Register. This register contains the result of the most
recent conversion completed on channel 6.
A/D Channel 7 Data Register. This register contains the result of the most
recent conversion completed on channel 7.
A/D Status Register. This register contains DONE and OVERRUN flags for
all of the A/D channels, as well as the A/D interrupt flag.
Type
Input
Input
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Description
Analog Inputs. The A/D converter cell can measure the voltage on any
of these input signals.
Remark: While the pins are 5 V tolerant in digital mode, the maximum
input voltage must not exceed V
analog inputs.
V
REF
; Reference voltage.
Chapter 25: LPC111x/LPC11Cxx ADC
Table
DD
when the pins are configured as
362.
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
Value
0x0000 0000
NA
-
0x0000 0100
NA
NA
NA
NA
NA
NA
NA
NA
0
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