LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 51

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
3.12 Flash memory access
UM10398
User manual
3.11.4.1 Normal mode
3.11.4.2 Power-down mode
In normal mode the post divider is enabled, giving a 50% duty cycle clock with the
following frequency relations:
To select the appropriate values for M and P, it is recommended to follow these steps:
Table 46
SYSPLLCTRL register
system clock divider SYSAHBCLKDIV is set to one (see
Table 46.
In this mode, the internal current reference is turned off, the oscillator and the
phase-frequency detector are stopped, and the dividers enter a reset state. While in
Power-down mode, the lock output is be LOW to indicate that the PLL is not in lock. When
the Power-down mode is terminated by setting the SYSPLL_PD bit to zero in the
Power-down configuration register
asserts the lock signal HIGH once it has regained lock on the input clock.
Depending on the system clock frequency, access to the flash memory can be configured
with various access times by writing to the FLASHCFG register at address 0x4003 C010.
This register is part of the flash configuration block (see
Remark: Improper setting of this register may result in incorrect operation of the
LPC111x/LPC11Cxx flash memory.
PLL input
clock
sys_pllclkin
(FCLKIN)
12 MHz
12 MHz
12 MHz
1. Specify the input clock frequency FCLKIN.
2. Calculate M to obtain the desired output frequency FCLKOUT with
3. Find a value so that FCCO = 2  P  FCLKOUT.
4. Verify that all frequencies and divider values conform to the limits specified in
5. Ensure that FCLKOUT < 100 MHz.
M = FCLKOUT / FCLKIN.
Table
shows how to configure the PLL for a 12 MHz crystal oscillator using the
10.
PLL configuration examples
All information provided in this document is subject to legal disclaimers.
Main clock
(FCLKOUT)
48 MHz
36 MHz
24 MHz
FCLKOUT
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
(Table
10). The main clock is equivalent to the system clock if the
=
MSEL bits
Table 10
00011
00010
00001
M
(Table

FCLKIN
43), the PLL resumes its normal operation and
M divider
value
4
3
2
=

FCCO
PSEL bits
Table 10
01
10
10
Figure
Table



2

20).
6).
P

P divider
value
2
4
4
UM10398
© NXP B.V. 2012. All rights reserved.
192 MHz
288 MHz
192 MHz
FCCO
frequency
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