LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 361

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 320: Capture Control Register (TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address
UM10398
User manual
Bit
1
2
31:3
Symbol
CAP0FE
CAP0I
-
0x4001 8028) bit description
20.7.10 External Match Register (TMR32B0EMR and TMR32B1EMR)
20.7.9 Capture Register (TMR32B0CR0 - address 0x4001 402C and
Value Description
1
0
1
0
TMR32B1CR0 - address 0x4001 802C)
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
Table 321: Capture registers (TMR32B0CR0, addresses 0x4001 402C and TMR32B1CR0,
The External Match Register provides both control and status of the external match pins
CAP32Bn_MAT[3:0].
If the match outputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules
controlled PWM outputs” on page
Bit
31:0
Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
Enabled
Disabled
Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will
generate an interrupt.
Enabled
Disabled
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Symbol
CAP
addresses 0x4001 802C) bit description
Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit counter/timer
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Description
Timer counter capture value.
365).
(Section 20.7.13 “Rules for single edge
UM10398
© NXP B.V. 2012. All rights reserved.
361 of 538
Reset
value
0
0
NA
Reset
value
0