LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 463

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.4.5.1.1 Wait for interrupt
28.4.5.1.2 Wait for event
28.4.5.1 Entering sleep mode
28.4.5 Power management
Remark: If lockup state occurs in the NMI handler a subsequent NMI does not cause the
processor to leave lockup state.
The Cortex-M0 processor sleep modes reduce power consumption:
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see
Section
This section describes the mechanisms for entering sleep mode and the conditions for
waking up from sleep mode.
This section describes the mechanisms software can use to put the processor into sleep
mode.
The system can generate spurious wake-up events, for example a debug operation wakes
up the processor. Therefore software must be able to put the processor back into sleep
mode after such an event. A program might have an idle loop to put the processor back in
to sleep mode.
The Wait For Interrupt instruction, WFI, causes immediate entry to sleep mode. When the
processor executes a WFI instruction it stops executing instructions and enters sleep
mode. See
Remark: The WFE instruction is not implemented on the LPC111x/LPC11Cxx.
The Wait For Event instruction, WFE, causes entry to sleep mode conditional on the value
of a one-bit event register. When the processor executes a WFE instruction, it checks the
value of the event register:
0 — The processor stops executing instructions and enters sleep mode
1 — The processor sets the register to zero and continues executing instructions without
entering sleep mode.
See
If the event register is 1, this indicates that the processor must not enter sleep mode on
execution of a WFE instruction. Typically, this is because of the assertion of an external
event, or because another processor in the system has executed a SEV instruction, see
Section
•
•
a sleep mode, that stops the processor clock
a Deep-sleep mode.
Section 28–28.5.7.11
28–28.6.3.5.
28–28.5.7.9. Software cannot access this register directly.
Section 28–28.5.7.12
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
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Rev. 12 — 24 September 2012
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