LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 341

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 295. Register overview: 16-bit counter/timer 0 CT16B0 (base address 0x4000 C000)
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UM10398
User manual
TMR16B0IR
TMR16B0TCR
TMR16B0TC
TMR16B0PR
TMR16B0PC
TMR16B0MCR
TMR16B0MR0
TMR16B0MR1
TMR16B0MR2
TMR16B0MR3
TMR16B0CCR
TMR16B0CR0
TMR16B0CR1
-
TMR16B0EMR
-
TMR16B0CTCR
TMR16B0PWMC R/W
Name
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
-
-
Access Address
R/W
R/W
R/W
R/W
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034 -
0x038
0x03C
0x040 -
0x06C
0x070
0x074
Description
Interrupt Register (IR). The IR can be written to clear interrupts. The IR
can be read to identify which of five possible interrupt sources are
pending.
Timer Control Register (TCR). The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset through
the TCR.
Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of
PCLK. The TC is controlled through the TCR.
Prescale Register (PR). When the Prescale Counter (below) is equal to
this value, the next clock increments the TC and clears the PC.
Prescale Counter (PC). The 16-bit PC is a counter which is incremented
to the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
Match Control Register (MCR). The MCR is used to control if an interrupt
is generated and if the TC is reset when a Match occurs.
Match Register 0 (MR0). MR0 can be enabled through the MCR to reset
the TC, stop both the TC and PC, and/or generate an interrupt every time
MR0 matches the TC.
Match Register 1 (MR1). See MR0 description.
Match Register 2 (MR2). See MR0 description.
Match Register 3 (MR3). See MR0 description.
Capture Control Register (CCR). The CCR controls which edges of the
capture inputs are used to load the Capture Registers and whether or not
an interrupt is generated when a capture takes place.
Capture Register 0 (CR0). CR0 is loaded with the value of TC when
there is an event on the CT16B0_CAP0 input.
Capture Register 1 (CR1). CR1 is loaded with the value of TC when
there is an event on the CT16B0_CAP1 input.
Reserved
External Match Register (EMR). The EMR controls the match function
and the external match pins CT16B0_MAT[2:0].
Reserved
Count Control Register (CTCR). The CTCR selects between Timer and
Counter mode, and in Counter mode selects the signal and edge(s) for
counting.
PWM Control Register (PWMCON). The PWMCON enables PWM mode
for the external match pins CT16B0_MAT[2:0].
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1
UM10398
© NXP B.V. 2012. All rights reserved.
0
0
0
341 of 538
Reset
value
0
0
0
0
0
0
0
0
0
0
-
0
-
0
0
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