LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 357

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 312. Register overview: 32-bit counter/timer 1 CT32B1 (base address 0x4001 8000)
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Table 313: Interrupt Register (TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000) bit
UM10398
User manual
Name
TMR32B1MCR
TMR32B1MR0
TMR32B1MR1
TMR32B1MR2
TMR32B1MR3
TMR32B1CCR
TMR32B1CR0
TMR32B1EMR
-
TMR32B1CTCR
TMR32B1PWMC R/W
Bit
0
1
2
3
4
31:5
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
description
Symbol
MR0 Interrupt
MR1 Interrupt
MR2 Interrupt
MR3 Interrupt
CR0 Interrupt
-
20.7.1 Interrupt Register (TMR32B0IR and TMR32B1IR)
20.7.2 Timer Control Register (TMR32B0TCR and TMR32B1TCR)
Access
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
-
R/W
The Interrupt Register consists of four bits for the match interrupts and one bit for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect.
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
offset
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x03C
0x040 -
0x06C
0x070
0x074
Address
Description
Interrupt flag for match channel 0.
Interrupt flag for match channel 1.
Interrupt flag for match channel 2.
Interrupt flag for match channel 3.
Interrupt flag for capture channel 0 event.
Reserved
Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit counter/timer
Description
Match Control Register (MCR). The MCR is used to control if an
interrupt is generated and if the TC is reset when a Match occurs.
Match Register 0 (MR0). MR0 can be enabled through the MCR to reset
the TC, stop both the TC and PC, and/or generate an interrupt every
time MR0 matches the TC.
Match Register 1 (MR1). See MR0 description.
Match Register 2 (MR2). See MR0 description.
Match Register 3 (MR3). See MR0 description.
Capture Control Register (CCR). The CCR controls which edges of the
capture inputs are used to load the Capture Registers and whether or
not an interrupt is generated when a capture takes place.
Capture Register 0 (CR0). CR0 is loaded with the value of TC when
there is an event on the CT32B1_CAP0 input.
External Match Register (EMR). The EMR controls the match function
and the external match pins CT32B1_MAT[3:0].
reserved
Count Control Register (CTCR). The CTCR selects between Timer and
Counter mode, and in Counter mode selects the signal and edge(s) for
counting.
PWM Control Register (PWMCON). The PWMCON enables PWM
mode for the external match pins CT32B1_MAT[3:0].
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
…continued
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0
0
0
0
0
-
0
0
0
Reset
value
0
0
0
0
0
-
0
0
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