LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 49

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
3.11 System PLL functional description
UM10398
User manual
Fig 10. System PLL block diagram
sys_osc_clk
irc_osc_clk
SYSPLLCLKSEL
3.11.1 Lock detector
10. Use the ARM WFI instruction to enter Deep-sleep mode.
The LPC111x/LPC11Cxx uses the system PLL to create the clocks for the core and
peripherals.
The block diagram of this PLL is shown in
to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This
block compares the phase and frequency of its inputs, and generates a control signal
when phase and/ or frequency do not match. The loop filter filters these control signals
and drives the current controlled oscillator (CCO), which generates the main clock and
optionally two additional phases. The CCO frequency range is 156 MHz to
320 MHz.These clocks are either divided by 2P by the programmable post divider to
create the output clock(s), or are sent directly to the output(s). The main output clock is
then divided by M by the programmable feedback divider to generate the feedback clock.
The output signal of the phase-frequency detector is also monitored by the lock detector,
to signal when the PLL has locked on to the input clock.
Remark: The divider values for P and M must be selected so that the PLL output clock
frequency FCLKOUT is lower than 100 MHz.
The lock detector measures the phase difference between the rising edges of the input
and feedback clocks. Only when this difference is smaller than the so called “lock
criterion” for more than eight consecutive input clock periods, the lock output switches
from low to high. A single too large phase difference immediately resets the counter and
causes the lock signal to drop (if it was high). Requiring eight phase measurements in a
8. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register
9. Start the counter/timer.
PFD
analog section
DETECT
LOCK
All information provided in this document is subject to legal disclaimers.
MSEL<4:0>
/M
pd
cd
5
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
pd
LOCK
Figure
PSEL<1:0>
10. The input frequency range is 10 MHz
2
/2P
pd
cd
UM10398
© NXP B.V. 2012. All rights reserved.
(Table
FCLKOUT
452).
49 of 538