LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 211

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
13.5.15.1.1 Example 1: UART_PCLK = 14.7456 MHz, BR = 9600
13.5.15.1.2 Example 2: UART_PCLK = 12 MHz, BR = 115200
13.5.16 UART Transmit Enable Register (U0TER - 0x4000 8030)
Table 200. Fractional Divider setting look-up table
According to the provided algorithm DL
= 96. Since this DL
DLL = 96.
According to the provided algorithm DL
6.51. This DL
parameter. Using an initial estimate of FR
is recalculated as FR
and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up
table.
The closest value for FRest = 1.628 in the look-up
equivalent to DIVADDVAL = 5 and MULVAL = 8.
Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4,
DIVADDVAL = 5, and MULVAL = 8. According to
115384. This rate has a relative error of 0.16% from the originally specified 115200.
In addition to being equipped with full hardware flow control (auto-cts and auto-rts
mechanisms described above), U0TER enables implementation of software flow control.
When TxEn = 1, UART transmitter will keep sending data as long as they are available. As
soon as TxEn becomes 0, UART transmission will stop.
FR
1.000
1.067
1.071
1.077
1.083
1.091
1.100
1.111
1.125
1.133
1.143
1.154
1.167
1.182
1.200
1.214
1.222
1.231
DivAddVal/
MulVal
0/1
1/15
1/14
1/13
1/12
1/11
1/10
1/9
1/8
2/15
1/7
2/13
1/6
2/11
1/5
3/14
2/9
3/13
est
All information provided in this document is subject to legal disclaimers.
is not an integer number and the next step is to estimate the FR
est
Rev. 12 — 24 September 2012
est
is an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and
FR
1.250
1.267
1.273
1.286
1.300
1.308
1.333
1.357
1.364
1.375
1.385
1.400
1.417
1.429
1.444
1.455
1.462
1.467
= 1.628. Since FR
DivAddVal/
MulVal
1/4
4/15
3/11
2/7
3/10
4/13
1/3
5/14
4/11
3/8
5/13
2/5
5/12
3/7
4/9
5/11
6/13
7/15
est
est
est
= PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600)
= PCLK/(16 x BR) = 12 MHz / (16 x 115200) =
est
= 1.5 a new DL
= 1.628 is within the specified range of 1.1
FR
1.500
1.533
1.538
1.545
1.556
1.571
1.583
1.600
1.615
1.625
1.636
1.643
1.667
1.692
1.700
1.714
1.727
1.733
Chapter 13: LPC111x/LPC11Cxx UART
Equation
Table 200
DivAddVal/
MulVal
1/2
8/15
7/13
6/11
5/9
4/7
7/12
3/5
8/13
5/8
7/11
9/14
2/3
9/13
7/10
5/7
8/11
11/15
3, the UART’s baud rate is
est
is FR = 1.625. It is
= 4 is calculated and FR
FR
1.750
1.769
1.778
1.786
1.800
1.818
1.833
1.846
1.857
1.867
1.875
1.889
1.900
1.909
1.917
1.923
1.929
1.933
UM10398
© NXP B.V. 2012. All rights reserved.
DivAddVal/
MulVal
3/4
10/13
7/9
11/14
4/5
9/11
5/6
11/13
6/7
13/15
7/8
8/9
9/10
10/11
11/12
12/13
13/14
14/15
211 of 538
est