LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 405

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
25.6 Operation
UM10398
User manual
25.5.5 A/D Status Register (AD0STAT - 0x4001 C030)
25.6.1 Hardware-triggered conversion
25.6.2 Interrupts
25.6.3 Accuracy vs. digital receiver
The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel
are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found
in ADSTAT.
Table 367. A/D Status Register (AD0STAT - address 0x4001 C030) bit description
If the BURST bit in the ADCR0 is 0 and the START field contains 010-111, the A/D
converter will start a conversion when a transition occurs on a selected pin or timer match
signal.
An interrupt is requested to the interrupt controller when the ADINT bit in the ADSTAT
register is 1. The ADINT bit is one when any of the DONE bits of A/D channels that are
enabled for interrupts (via the ADINTEN register) are one. Software can use the Interrupt
Enable bit in the interrupt controller that corresponds to the ADC to control whether this
results in an interrupt. The result register for an A/D channel that is generating an interrupt
must be read in order to clear the corresponding DONE flag.
While the A/D converter can be used to measure the voltage on any ADC input pin,
regardless of the pin’s setting in the IOCON block, selecting the ADC in the IOCON
registers function improves the conversion accuracy by disabling the pin’s digital receiver
(see also
Bit
7:0
15:8
16
31:17 -
Symbol
DONE
OVERRUN
ADINT
Section
All information provided in this document is subject to legal disclaimers.
7.3.4).
Rev. 12 — 24 September 2012
Description
These bits mirror the DONE status flags that appear in the result
register for each A/D channel n.
These bits mirror the OVERRRUN status flags that appear in the
result register for each A/D channel n. Reading ADSTAT allows
checking the status of all A/D channels simultaneously.
This bit is the A/D interrupt flag. It is one when any of the
individual A/D channel Done flags is asserted and enabled to
contribute to the A/D interrupt via the ADINTEN register.
Reserved. Unused, always 0.
Chapter 25: LPC111x/LPC11Cxx ADC
UM10398
© NXP B.V. 2012. All rights reserved.
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Reset
Value
0
0
0
0