LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 471

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.3.6.1 The condition flags
28.5.3.6.2 Condition code suffixes
28.5.3.6 Conditional execution
Most data processing instructions update the condition flags in the Application Program
Status Register (APSR) according to the result of the operation, see
instructions update all flags, and some only update a subset. If a flag is not updated, the
original value is preserved. See the instruction descriptions for the flags they affect.
You can execute a conditional branch instruction, based on the condition flags set in
another instruction, either:
On the Cortex-M0 processor, conditional execution is available by using conditional
branches.
This section describes:
The APSR contains the following condition flags:
N — Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
Z — Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
C — Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
V — Set to 1 when the operation caused overflow, cleared to 0 otherwise.
For more information about the APSR see
A carry occurs:
Overflow occurs when the sign of the result, in bit[31], does not match the sign of the
result had the operation been performed at infinite precision, for example:
The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except
that the result is discarded. See the instruction descriptions for more information.
Conditional branch is shown in syntax descriptions as B{cond}. A branch instruction with a
condition code is only taken if the condition code flags in the APSR meet the specified
condition, otherwise the branch instruction is ignored. shows the condition codes to use.
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immediately after the instruction that updated the flags
after any number of intervening instructions that have not updated the flags.
Section 28.5.3.6.1 “The condition flags”
Section 28.5.3.6.2 “Condition code
if the result of an addition is greater than or equal to 2
if the result of a subtraction is positive or zero
as the result of a shift or rotate instruction.
if adding two negative values results in a positive value
if adding two positive values results in a negative value
if subtracting a positive value from a negative value generates a positive value
if subtracting a negative value from a positive value generates a negative value.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
suffixes”.
Section
28–28.4.1.3.5.
32
Section
UM10398
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