LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 191

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
13.4 Pin description
13.5 Register description
Table 183. Register overview: UART (base address: 0x4000 8000)
UM10398
User manual
U0DLM
U0IER
U0IIR
U0FCR
Name
U0RBR
U0THR
U0DLL
Access Address
RO
WO
R/W
R/W
R/W
RO
WO
Table 182. UART pin description
[1]
The DSR, DCD, and RI modem inputs are multiplexed to two different pin locations. Use
the IOCON_LOC registers (see
on the LQFP48 pin package in addition to selecting the function in the IOCON registers.
The DTR output is available in two pin locations as well. The output value of the DTR pin
is driven in both locations identically, and the DTR function at any location can be selected
simply by selecting the function in the IOCON register for that pin location.
The UART contains registers organized as shown in
Bit (DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches.
The reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Pin
RXD
TXD
RTS
DTR
DSR
CTS
DCD
RI
offset
0x000
0x000
0x000
0x004
0x004
0x008
0x008
[1]
LQFP48 packages only.
[1]
[1]
Type
Input
Output Serial Output. Serial transmit data.
Output Request To Send. RS-485 direction control pin.
Output Data Terminal Ready.
Input
Input
Input
Input
Description
Receiver Buffer Register. Contains the next received character to be read.
(DLAB=0)
Transmit Holding Register. The next character to be transmitted is written
here. (DLAB=0)
Divisor Latch LSB. Least significant byte of the baud rate divisor value. The
full divisor is used to generate a baud rate from the fractional rate divider.
(DLAB=1)
Divisor Latch MSB. Most significant byte of the baud rate divisor value. The
full divisor is used to generate a baud rate from the fractional rate divider.
(DLAB=1)
Interrupt Enable Register. Contains individual interrupt enable bits for the 7
potential UART interrupts. (DLAB=0)
Interrupt ID Register. Identifies which interrupt(s) are pending.
FIFO Control Register. Controls UART FIFO usage and modes.
All information provided in this document is subject to legal disclaimers.
Description
Serial Input. Serial receive data.
Data Set Ready.
Clear To Send.
Data Carrier Detect.
Ring Indicator.
Rev. 12 — 24 September 2012
Section
7.4) to select a physical location for each function
Chapter 13: LPC111x/LPC11Cxx UART
Table
183. The Divisor Latch Access
UM10398
© NXP B.V. 2012. All rights reserved.
191 of 538
Reset
value
NA
NA
0x01
0x00
0x00
0x01
0x00