LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 493

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LPC1112FHN33/203,5

Manufacturer Part Number
LPC1112FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC1112FHN33/203,5

Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1112
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
16 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
NXP Semiconductors
UM10398
User manual
28.5.7.6.4 Condition flags
28.5.7.6.5 Examples
28.5.7.7.1 Syntax
28.5.7.7.2 Operation
28.5.7.7.3 Restrictions
28.5.7.7.4 Condition flags
28.5.7.7.5 Examples
28.5.7.8.1 Syntax
28.5.7.8.2 Operation
28.5.7.8.3 Restrictions
28.5.7.7 MSR
28.5.7.8 NOP
This instruction does not change the flags.
Move the contents of a general-purpose register into the specified special register.
MSR spec_reg, Rn
where:
MSR updates one of the special registers with the value from the register specified by Rn.
See
In this instruction, Rn must not be SP and must not be PC.
This instruction updates the flags explicitly based on the value in Rn.
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register
No Operation.
NOP
NOP performs no operation and is not guaranteed to be time consuming. The processor
might remove it from the pipeline before it reaches the execution stage.
Use NOP for padding, for example to place the subsequent instructions on a 64-bit
boundary.
There are no restrictions.
MRS R0, PRIMASK ; Read PRIMASK value and write it to R0
Rn is the general-purpose source register.
spec_reg is the special-purpose destination register: APSR, IPSR, EPSR, IEPSR,
IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
Section
28–28.5.7.6.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
UM10398
© NXP B.V. 2012. All rights reserved.
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