LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 46

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.9.3.3 Wake-up from Deep-sleep mode
3.9.4 Deep power-down mode
The microcontroller can wake up from Deep-sleep mode in the following ways:
Remark: If the watchdog oscillator is running in Deep-sleep mode, its frequency
determines the wake-up time causing the wake-up time to be longer than waking up with
the IRC.
In Deep power-down mode, power and clocks are shut off to the entire chip with the
exception of the WAKEUP pin.
During Deep power-down mode, the contents of the SRAM and registers are not retained
except for a small amount of data which can be stored in the five 32-bit general purpose
registers of the PMU block.
2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG
3. Select the power configuration after wake-up in the PDAWAKECFG
4. If an external pin is used for wake-up, enable and clear the wake-up pin in the start
5. In the SYSAHBCLKCTRL register
6. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register
7. Use the ARM WFI instruction.
•
•
•
•
•
register.
a. If a timer-controlled wake-up is needed, ensure that the watchdog oscillator is
b. If no timer-controlled wake-up is needed and the watchdog oscillator is shut down,
register.
logic registers
counter/timer or WDT if needed.
Signal on an external pin. For this purpose, pins PIO0_0 to PIO0_11 and PIO1_0 can
be enabled as inputs to the start logic. The start logic does not require any clocks and
generates the interrupt if enabled in the NVIC to wake up from Deep-sleep mode.
Input signal to the start logic created by a match event on one of the general purpose
timer external match outputs. The pin holding the timer match function must be
enabled as start logic input in the NVIC, the corresponding timer must be enabled in
the SYSAHBCLKCTRL register, and the watchdog oscillator must be running in
Deep-sleep mode (for details see
Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the
PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL
register
Reset from the watchdog timer. In this case, the watchdog oscillator must be running
in Deep-sleep mode (see PDSLEEPCFG register), and the WDT must be enabled in
the SYSAHBCLKCTRL register.
A reset signal from the external RESET pin.
powered in the PDRUNCFG register and switch the clock source to WD oscillator
in the MAINCLKSEL register
ensure that the IRC is powered in the PDRUNCFG register and switch the clock
source to IRC in the MAINCLKSEL register
system clock is shut down glitch-free.
(Table
All information provided in this document is subject to legal disclaimers.
(Table 36
33).
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
to
Table
(Table
39), and enable the start logic interrupt in the NVIC.
Section
(Table
18).
21), disable all peripherals except
3.10.3).
(Table
18). This ensures that the
UM10398
© NXP B.V. 2012. All rights reserved.
(Table
(Table
(Table
42)
452).
46 of 538
41)