LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 234

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
15.6 Pin description
15.7 Register description
Table 218. Register overview: I
UM10398
User manual
Name
I2C0CONSET R/W
I2C0STAT
I2C0DAT
I2C0ADR0
I2C0SCLH
I2C0SCLL
I2C0CONCLR WO
I2C0MMCTRL R/W
I2C0ADR1
I2C0ADR2
Access Address
RO
R/W
R/W
R/W
R/W
R/W
R/W
Table 217. I
The I
IOCON_PIO0_5
Fast-mode Plus, rates above 400 kHz and up to 1 MHz may be selected. The I
are open-drain outputs and fully compatible with the I
Pin
SDA
SCL
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
2
C-bus pins must be configured through the IOCON_PIO0_4
2
C (base address 0x4000 0000)
2
C-bus pin description
Description
I2C Control Set Register. When a one is written to a bit of this register,
the corresponding bit in the I
no effect on the corresponding bit in the I
I2C Status Register. During I
status codes that allow software to determine the next action needed.
I2C Data Register. During master or slave transmit mode, data to be
transmitted is written to this register. During master or slave receive
mode, data that has been received may be read from this register.
I2C Slave Address Register 0. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
SCH Duty Cycle Register High Half Word. Determines the high time of
the I
SCL Duty Cycle Register Low Half Word. Determines the low time of
the I
frequency generated by an I
mode.
I2C Control Clear Register. When a one is written to a bit of this register,
the corresponding bit in the I
has no effect on the corresponding bit in the I
Monitor mode control register.
I2C Slave Address Register 1. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
I2C Slave Address Register 2. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
Type
Input/Output
Input/Output
All information provided in this document is subject to legal disclaimers.
(Table
2
2
C clock.
C clock. I2nSCLL and I2nSCLH together determine the clock
Rev. 12 — 24 September 2012
68) registers for Standard/ Fast-mode or Fast-mode Plus. In
2
2
2
C interface in slave mode, and is not used in master
C interface in slave mode, and is not used in master
C interface in slave mode, and is not used in master
Description
I
I
2
2
C Serial Data
C Serial Clock
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
2
2
2
C master and certain times used in slave
C control register is set. Writing a zero has
C control register is cleared. Writing a zero
2
C operation, this register provides detailed
2
C control register.
2
C-bus specification.
2
C control register.
(Table
UM10398
© NXP B.V. 2012. All rights reserved.
67) and
2
C-bus pins
234 of 538
Reset
value
0x00
0xF8
0x00
0x00
0x04
0x04
NA
0x00
0x00
0x00
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