LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 481

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.5.2.1 Syntax
28.5.5.2.2 Operation
28.5.5.2.3 Restrictions
28.5.5.2.4 Condition flags
28.5.5.2.5 Examples
28.5.5.3.1 Syntax
28.5.5.3 ASR, LSL, LSR, and ROR
ANDS {Rd,} Rn, Rm
ORRS {Rd,} Rn, Rm
EORS {Rd,} Rn, Rm
BICS {Rd,} Rn, Rm
where:
The AND, EOR, and ORR instructions perform bitwise AND, exclusive OR, and inclusive
OR operations on the values in Rn and Rm.
The BIC instruction performs an AND operation on the bits in Rn with the logical negation
of the corresponding bits in the value of Rm.
The condition code flags are updated on the result of the operation, see
Section
In these instructions, Rd, Rn, and Rm must only specify R0-R7.
These instructions:
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, and Rotate Right.
ASRS {Rd,} Rm, Rs
ASRS {Rd,} Rm, #imm
LSLS {Rd,} Rm, Rs
LSLS {Rd,} Rm, #imm
•
•
Rd is the destination register.
Rn is the register holding the first operand and is the same as the destination register.
Rm second register.
ANDS R2, R2, R1
update the N and Z flags according to the result
do not affect the C or V flag.
ORRS R2, R2, R5
ANDS R5, R5, R8
EORS R7, R7, R6
BICS R0, R0, R1
28.5.3.6.1.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
UM10398
© NXP B.V. 2012. All rights reserved.
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