LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 451
LPC1112FHN33/203,5
Manufacturer Part Number
LPC1112FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1112FHN33/203,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1112
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
16 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
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UM10398
User manual
28.4.1.4 Exceptions and interrupts
28.4.1.5 Data types
28.4.1.6 The Cortex Microcontroller Software Interface Standard
Table 425. CONTROL register bit assignments
Handler mode always uses the MSP, so the processor ignores explicit writes to the active
stack pointer bit of the CONTROL register when in Handler mode. The exception entry
and return mechanisms update the CONTROL register.
In an OS environment, it is recommended that threads running in Thread mode use the
process stack and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode
to the PSP, use the MSR instruction to set the Active stack pointer bit to 1, see
Section
Remark: When changing the stack pointer, software must use an ISB instruction
immediately after the MSR instruction. This ensures that instructions after the ISB execute
using the new stack pointer. See
The Cortex-M0 processor supports interrupts and system exceptions. The processor and
the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An
interrupt or exception changes the normal flow of software control. The processor uses
handler mode to handle all exceptions except for reset. See
Section 28–28.4.3.6.2
The NVIC registers control interrupt handling. See
information.
The processor:
ARM provides the Cortex Microcontroller Software Interface Standard (CMSIS) for
programming Cortex-M0 microcontrollers. The CMSIS is an integrated part of the device
driver library.
Bits
[31:2]
[1]
[0]
•
•
supports the following data types:
– 32-bit words
– 16-bit halfwords
– 8-bit bytes
manages all data memory accesses as little-endian. Instruction memory and Private
Peripheral Bus (PPB) accesses are always little-endian. See
more information.
28–28.5.7.6.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Name
-
Active stack
pointer
-
Rev. 12 — 24 September 2012
for more information.
Section
Function
Reserved
Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
Reserved.
28–28.5.7.5.
Section 28–28.6.2
Section 28–28.4.3.6.1
Section 28–28.4.2.1
for more
UM10398
© NXP B.V. 2012. All rights reserved.
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