LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 196

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
If the IntStatus bit is one and no interrupt is pending and the IntId bits will be zero. If the
IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the
type of interrupt and handling as described in
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The U0IIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
The UART RLS interrupt (U0IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART Rx error
condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared
upon a U0LSR read.
The UART RDA interrupt (U0IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (U0IIR[3:1] = 110). The RDA is activated when the UART Rx FIFO reaches the
trigger level defined in U0FCR7:6 and is reset when the UART Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (U0IIR[3:1] = 110) is a second level interrupt and is set when the UART
Rx FIFO contains at least one character and no UART Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UART Rx FIFO activity (read or write of UART RSR) will
clear the interrupt. This interrupt is intended to flush the UART RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
Table 190. UART Interrupt Handling
U0IIR[3:0]
value
0001
0110
0100
[1]
Priority Interrupt
-
Highest RX Line
Second RX Data
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type
None
Status /
Error
Available
Rev. 12 — 24 September 2012
Interrupt source
None
OE
Rx data available or trigger level reached in FIFO
(U0FCR0=1)
[2]
or PE
[2]
or FE
Table
[2]
Chapter 13: LPC111x/LPC11Cxx UART
or BI
190. Given the status of U0IIR[3:0], an
[2]
UM10398
© NXP B.V. 2012. All rights reserved.
Interrupt
reset
-
U0LSR
Read
U0RBR
Read
UART FIFO
drops below
trigger level
196 of 538
[2]
[3]
or