LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 285

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
16.6.1.7 CAN baud rate prescaler extension register
16.6.2 Message interface registers
Table 250. CAN test register (CANTEST, address 0x4005 0014) bit description
Table 251. CAN baud rate prescaler extension register (CANBRPE, address 0x4005 0018) bit
There are two sets of interface registers which are used to control the CPU access to the
Message RAM. The interface registers avoid conflicts between CPU access to the
Message RAM and CAN message reception and transmission by buffering the data to be
transferred. A complete Message Object (see
Object may be transferred between the Message RAM and the IFx Message Buffer
registers in one single transfer.
The function of the two interface register sets is identical (except for test mode Basic).
One set of registers may be used for data transfer to the Message RAM while the other
set of registers may be used for the data transfer from the Message RAM, allowing both
processes to be interrupted by each other.
Each set of interface registers consists of message buffer registers controlled by their own
command registers. The command mask register specifies the direction of the data
transfer and which parts of a message object will be transferred. The command request
register is used to select a message object in the message RAM as target or source for
the transfer and to start the action specified in the command mask register.
Bit
6:5
7
31:8
Bit
3:0
31:4
Symbol
TX
RX
-
Symbol
BRPE
-
description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
0
1
Description
Baud rate prescaler extension
By programming BRPE the Baud Rate Prescaler can be
extended to values up to 1023. Hardware interprets the
value as the value of BRPE (MSBs) and BRP (LSBs) plus
one. Allowed values are 0 to 15.
Reserved
Rev. 12 — 24 September 2012
Description
Control of CAN_TXD pins
Level at the CAN_TXD pin is controlled by the
CAN controller. This is the value at reset.
The sample point can be monitored at the
CAN_TXD pin.
CAN_TXD pin is driven LOW/dominant.
CAN_TXD pin is driven HIGH/recessive.
Monitors the actual value of the CAN_RXD
pin.
The CAN bus is recessive (CAN_RXD = ‘1’).
The CAN bus is dominant (CAN_RXD = ‘0’).
R/W
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
Section
16.6.2.1) or parts of the Message
Reset
value
00
0
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
0x0000 R/W
-
Access
R/W
R
-
Access
-
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