LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 232

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

15.1 How to read this chapter
15.2 Basic configuration
15.3 Features
15.4 Applications
UM10398
User manual
The I
The I2C-bus is interface is not available on part LPC1112FDH20/102.
The I
Interfaces to external I
other microcontrollers, etc.
1. Pins: The I2C pin functions and the I2C mode are configured in the IOCONFIG
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 5
3. Reset: Before accessing the I2C block, ensure that the I2C_RST_N bit (bit 1) in the
•
•
•
•
•
•
•
•
•
•
•
UM10398
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
Rev. 12 — 24 September 2012
register block
PRESETCTRL register
block.
Standard I
Master/Slave.
Arbitration is handled between simultaneously transmitting masters without corruption
of serial data on the bus.
Programmable clock allows adjustment of I
Data transfer is bidirectional between masters and slaves.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization is used as a handshake mechanism to suspend and
resume serial transfer.
Supports Fast-mode Plus.
Optional recognition of up to four distinct slave addresses.
Monitor mode allows observing all I
I
The I
2
2
2
C-bus can be used for test and diagnostic purposes.
C-bus block is identical for all LPC111x, LPC11D14, and LPC11Cxx parts.
C-bus interface is configured using the following registers:
2
C-bus contains a standard I
2
C-compliant bus interfaces may be configured as Master, Slave, or
All information provided in this document is subject to legal disclaimers.
(Section
Rev. 12 — 24 September 2012
2
C standard parts, such as serial RAMs, LCDs, tone generators,
7.4,
(Table
Table 67
9) is set to 1. This de-asserts the reset signal to the I2C
2
C-compliant bus interface with two pins.
2
C-bus traffic, regardless of slave address.
and
Table
2
C transfer rates.
68).
© NXP B.V. 2012. All rights reserved.
User manual
(Table
232 of 538
21).