LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 213

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
13.5.18 UART RS485 Address Match register (U0RS485ADRMATCH - 0x4000
13.5.19 UART1 RS485 Delay value register (U0RS485DLY - 0x4000 8054)
13.5.20 RS-485/EIA-485 modes of operation
Table 202. UART RS485 Control register (U0RS485CTRL - address 0x4000 804C) bit
8050)
The U0RS485ADRMATCH register contains the address match value for RS-485/EIA-485
mode.
Table 203. UART RS485 Address Match register (U0RS485ADRMATCH - address
The user may program the 8-bit RS485DLY register with a delay between the last stop bit
leaving the TXFIFO and the de-assertion of RTS (or DTR). This delay time is in periods of
the baud clock. Any delay time from 0 to 255 bit times may be programmed.
Table 204. UART RS485 Delay value register (U0RS485DLY - address 0x4000 8054) bit
The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.
Bit
4
5
31:6 -
Bit
7:0
31:8
Bit
7:0
31:8
Symbol
DCTRL
OINV
Symbol
DLY
-
Symbol
ADRMATCH
-
description
0x4000 8050) bit description
description
All information provided in this document is subject to legal disclaimers.
Description
Contains the direction control (RTS or DTR) delay value. This
register works in conjunction with an 8-bit counter.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Value
0
1
0
1
-
Rev. 12 — 24 September 2012
…continued
Description
Contains the address match value.
Reserved
Description
Auto direction control enable.
Disable Auto Direction Control.
Enable Auto Direction Control.
Polarity control. This bit reverses the polarity of
the direction control signal on the RTS (or DTR)
pin.
The direction control pin will be driven to logic 0
when the transmitter has data to be sent. It will be
driven to logic 1 after the last bit of data has been
transmitted.
The direction control pin will be driven to logic 1
when the transmitter has data to be sent. It will be
driven to logic 0 after the last bit of data has been
transmitted.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Chapter 13: LPC111x/LPC11Cxx UART
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0x00
-
Reset value
0x00
NA
Reset
value
0
0
NA
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