LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 375

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 336: Capture Control Register (TMR32B0CCR - address 0x4001 4028 and TMR32B1CCR - address
UM10398
User manual
Bit
0
1
2
3
4
5
31:6
Symbol
CAP0RE
CAP0FE
CAP0I
CAP1RE
CAP1FE
CAP1I
-
0x4001 8028) bit description
21.7.8 Capture Control Register (TMR32B0CCR and TMR32B1CCR)
Value Description
1
0
1
0
1
0
1
0
1
0
1
0
Table 335: Match registers (TMR32B0MR0 to 3, addresses 0x4001 4018 to 24 and
The Capture Control Register is used to control whether the Capture Register is loaded
with the value in the Timer Counter when the capture event occurs, and whether an
interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, “n” represents the Timer number, 0 or 1.
Bit
31:0
Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
Enabled
Disabled
Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
Enabled
Disabled
Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will
generate an interrupt.
Enabled
Disabled
Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will
cause CR1 to be loaded with the contents of TC.
Enabled
Disabled
Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will
cause CR1 to be loaded with the contents of TC.
Enabled
Disabled
Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will
generate an interrupt.
Enabled
Disabled
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Symbol
MATCH
TMR32B1MR0 to 3, addresses 0x4001 8018 to 24) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
Description
Timer counter match value.
UM10398
© NXP B.V. 2012. All rights reserved.
375 of 538
Reset
value
0
0
0
0
0
0
NA
Reset
value
0