LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 465

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 429. Cortex-M0 instructions
UM10398
User manual
Mnemonic
ADCS
ADD{S}
ADR
ANDS
ASRS
B{cc}
BICS
BKPT
BL
BLX
BX
CMN
CMP
CPSID
CPSIE
DMB
DSB
EORS
ISB
LDM
LDR
LDR
LDRB
LDRH
LDRSB
LDRSH
LSLS
U
MOV{S}
MRS
MSR
MULS
MVNS
Operands
{Rd,} Rn, Rm
{Rd,} Rn, <Rm|#imm>
Rd, label
{Rd,} Rn, Rm
{Rd,} Rm, <Rs|#imm>
label
{Rd,} Rn, Rm
#imm
label
Rm
Rm
Rn, Rm
Rn, <Rm|#imm>
i
i
-
-
{Rd,} Rn, Rm
-
Rn{!}, reglist
Rt, label
Rt, [Rn, <Rm|#imm>]
Rt, [Rn, <Rm|#imm>]
Rt, [Rn, <Rm|#imm>]
Rt, [Rn, <Rm|#imm>]
Rt, [Rn, <Rm|#imm>]
{Rd,} Rn, <Rs|#imm>
{Rd,} Rn, <Rs|#imm>
Rd, Rm
Rd, spec_reg
spec_reg, Rm
Rd, Rn, Rm
Rd, Rm
For more information on the instructions and operands, see the instruction descriptions.
•
•
•
angle brackets, <>, enclose alternative forms of the operand
braces, {}, enclose optional operands and mnemonic parts
the Operands column is not exhaustive.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Brief description
Add with Carry
Add
PC-relative Address to Register
Bitwise AND
Arithmetic Shift Right
Branch {conditionally}
Bit Clear
Breakpoint
Branch with Link
Branch indirect with Link
Branch indirect
Compare Negative
Compare
Change Processor State, Disable
Interrupts
Change Processor State, Enable
Interrupts
Data Memory Barrier
Data Synchronization Barrier
Exclusive OR
Instruction Synchronization Barrier
Load Multiple registers, increment after
Load Register from PC-relative address -
Load Register with word
Load Register with byte
Load Register with halfword
Load Register with signed byte
Load Register with signed halfword
Logical Shift Left
Logical Shift Right
Move
Move to general register from special
register
Move to special register from general
register
Multiply, 32-bit result
Bitwise NOT
Rev. 12 — 24 September 2012
Flags
N,Z,C,V
N,Z,C,V
-
N,Z
N,Z,C
-
N,Z
-
-
-
-
N,Z,C,V
N,Z,C,V
-
-
-
-
N,Z
-
-
-
-
-
-
-
N,Z,C
N,Z,C
N,Z
-
N,Z,C,V
N,Z
N,Z
Reference
Section 28–28.5.5.1
Section 28–28.5.5.1
Section 28–28.5.4.1
Section 28–28.5.5.1
Section 28–28.5.5.3
Section 28–28.5.6.1
Section 28–28.5.5.2
Section 28–28.5.7.1
Section 28–28.5.6.1
Section 28–28.5.6.1
Section 28–28.5.6.1
Section 28–28.5.5.4
Section 28–28.5.5.4
Section 28–28.5.7.2
Section 28–28.5.7.2
Section 28–28.5.7.3
Section 28–28.5.7.4
Section 28–28.5.5.2
Section 28–28.5.7.5
Section 28–28.5.4.5
Section 28–28.5.4
Section 28–28.5.4
Section 28–28.5.4
Section 28–28.5.4
Section 28–28.5.4
Section 28–28.5.4
Section 28–28.5.5.3
Section 28–28.5.5.3
Section 28–28.5.5.5
Section 28–28.5.7.6
Section 28–28.5.7.7
Section 28–28.5.5.6
Section 28–28.5.5.5
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