LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 310

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
16.7.5.1 Bit time and bit rate
CAN supports bit rates in the range of lower than 1 kBit/s up to 1000 kBit/s. Each member
of the CAN network has its own clock generator, usually a quartz oscillator. The timing
parameter of the bit time (i.e. the reciprocal of the bit rate) can be configured individually
for each CAN node, creating a common bit rate even though the CAN nodes’ oscillator
periods (f
The frequencies of these oscillators are not absolutely stable, as small variations are
caused by changes in temperature or voltage and by deteriorating components. As long
as the variations remain inside a specific oscillator tolerance range (df), the CAN nodes
are able to compensate for the different bit rates by re-synchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments
The Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific,
programmable number of time quanta (see
(t
clock f and the Baud Rate Prescaler (BRP): t
is the frequency of the LPC11Cx system clock (see
The Synchronization Segment Sync_Seg is the part of the bit time where edges of the
CAN bus level are expected to occur; the distance between an edge that occurs outside of
Sync_Seg and the Sync_Seg is called the phase error of that edge. The Propagation
Time Segment Prop_Seg is intended to compensate for the physical delay times within
the CAN network. The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 surround
the Sample Point. The (Re-)Synchronization Jump Width (SJW) defines how far a
re-synchronization may move the Sample Point inside the limits defined by the Phase
Buffer Segments to compensate for edge phase errors.
Table 277
Bit time parameters are programmed through the CANBT register,
on bit timing and examples, see the C_CAN user’s manual, revision 1.2.
Table 277. Parameters of the C_CAN bit time
Parameter
BRP
SYNC_SEG
PROP_SEG
TSEG1
TSEG2
SJW
q
), which is the basic time unit of the bit time, is defined by the CAN controller’s system
osc
describes the minimum programmable ranges required by the CAN protocol.
) may be different.
All information provided in this document is subject to legal disclaimers.
Range
(1...32)
1t
(1...8)  t
(1...8)  t
(1...8)  t
(1...4)  t
q
Rev. 12 — 24 September 2012
q
q
q
q
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
Function
Defines the length of the time quantum t
Synchronization segment. Fixed length. Synchronization
of bus input to system clock.
Propagation time segment. Compensates for physical
delay times. This parameter is determined by the system
delay times in the C_CAN network.
Phase buffer segment 1. May be lengthened temporarily
by synchronization.
Phase buffer segment 2. May be shortened temporarily by
synchronization.
(Re-) synchronization jump width. May not be longer than
either phase buffer segment.
Table
q
= BRP / f
277). The length of the time quantum
Section
sys
. The C_CAN’s system clock f
16.2).
Table
UM10398
© NXP B.V. 2012. All rights reserved.
q
248. For details
.
(Figure
310 of 538
66).
sys