LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 239

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
15.7.6 I
15.7.7 I
SCLL and SCLH values should not necessarily be the same. Software can set different
duty cycles on SCL by setting these two registers. For example, the I
defines the SCL low time and high time at different values for a Fast-mode and Fast-mode
Plus I
The CONCLR register control clearing of bits in the CON register that controls operation
of the I
the I
Table 226. I
AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
CONSET register. Writing 0 has no effect.
SIC is the I
register. Writing 0 has no effect.
STAC is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the CONSET
register. Writing 0 has no effect.
I2ENC is the I
CONSET register. Writing 0 has no effect.
This register controls the Monitor mode which allows the I
the I
Bit
1:0
2
3
4
5
6
7
31:8 -
2
2
C Control Clear register (I2C0CONCLR - 0x4000 0018)
C Monitor mode control register (I2C0MMCTRL - 0x4000 001C)
2
2
C control register to be cleared. Writing a zero has no effect.
C bus without actually participating in traffic or interfering with the I
2
Symbol
-
AAC
SIC
-
STAC
I2ENC
-
C.
2
C interface. Writing a one to a bit of this register causes the corresponding bit in
2
2
C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the CONSET
C Control Clear register (I2C0CONCLR - 0x4000 0018) bit description
2
C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
All information provided in this document is subject to legal disclaimers.
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Assert acknowledge Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
START flag Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Reserved. The value read from a reserved bit is not defined.
2
2
C interrupt Clear bit.
C interface Disable bit.
Rev. 12 — 24 September 2012
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
2
C module to monitor traffic on
2
C-bus specification
UM10398
© NXP B.V. 2012. All rights reserved.
2
C bus.
Reset
value
NA
0
NA
0
0
NA
-
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