LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 403

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 363. A/D Control Register (AD0CR - address 0x4001 C000) bit description
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UM10398
User manual
Bit
26:24 START
27
31:28 -
Note that this does not require that the timer match function appear on a device pin.
Symbol
EDGE
25.5.2 A/D Global Data Register (AD0GDR - 0x4001 C004)
Value Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0
1
The A/D Global Data Register contains the result of the most recent A/D conversion. This
includes the data, DONE, and Overrun flags, and the number of the A/D channel to which
the data relates.
Table 364. A/D Global Data Register (AD0GDR - address 0x4001 C004) bit description
Bit
5:0
15:6
23:16 -
26:24 CHN
29:27 -
30
31
When the BURST bit is 0, these bits control whether and when an A/D conversion is
started:
No start (this value should be used when clearing PDN to 0).
Start conversion now.
Start conversion when the edge selected by bit 27 occurs on
PIO0_2/SSEL/CT16B0_CAP0.
Start conversion when the edge selected by bit 27 occurs on
PIO1_5/DIR/CT32B0_CAP0.
Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0
Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1
This bit is significant only when the START field contains 010-111. In these cases:
Start conversion on a rising edge on the selected CAP/MAT signal.
Start conversion on a falling edge on the selected CAP/MAT signal.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Symbol
-
V_VREF
OVERRUN
DONE
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
This bit is 1 in burst mode if the results of one or more conversions
Description
Reserved. These bits always read as zeroes.
When DONE is 1, this field contains a binary fraction representing
the voltage on the ADn pin selected by the SEL field, divided by
the voltage on the V
voltage on the ADn pin was less than, equal to, or close to that on
V
equal to, or greater than that on V
Reserved. These bits always read as zeroes.
These bits contain the channel from which the result bits V_VREF
were converted.
Reserved. These bits always read as zeroes.
was (were) lost and overwritten before the conversion that
produced the result in the V_VREF bits.
This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read and when the ADCR is written. If the
ADCR is written while a conversion is still in progress, this bit is
set and a new conversion is started.
SS
, while 0x3FF indicates that the voltage on ADn was close to,
DD
pin. Zero in the field indicates that the
Chapter 25: LPC111x/LPC11Cxx ADC
REF
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UM10398
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© NXP B.V. 2012. All rights reserved.
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Reset
Value
0
X
0
X
0
0
0
Reset
Value
0
0
NA