LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 408

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
26.3.2 Memory map after any reset
26.3.3 Criterion for Valid User Code
The bootloader code is executed every time the part is powered on or reset. The loader
can execute the ISP command handler or the user application code. A LOW level after
reset at the PIO0_1 pin is considered as an external hardware request to start the ISP
command handler either via UART or C_CAN, if present.
Remark: SRAM location 0x1000 0000 to 0x1000 0050 is not used by the bootloader and
the memory content in this area is retained during reset. SRAM memory is not retained
when the part powers down or enters Deep power-down mode.
If the C_CAN interface is present (LPC11Cx parts), the state of pin PIO0_3 at reset
together with a LOW level on pin PIO0_1 determines whether UART ISP or C_CAN ISP
routines are called:
Remark: On parts without C_CAN interface, the state of pin PIO0_3 does not matter.
Assuming that power supply pins are on their nominal levels when the rising edge on
RESET pin is generated, it may take up to 3 ms before PIO0_1 is sampled and the
decision whether to continue with user code or ISP handler is made. If PIO0_1 is sampled
low and the watchdog overflow flag is set, the external hardware request to start the ISP
command handler is ignored. If there is no request for the ISP command handler
execution (PIO0_1 is sampled HIGH after reset), a search is made for a valid user
program. If a valid user program is found then the execution control is transferred to it. If a
valid user program is not found, the auto-baud routine is invoked.
Remark: The sampling of pin PIO0_1 can be disabled through programming flash
location 0x0000 02FC (see
The boot block is 16 kB in size. The boot block is located in the memory region starting
from the address 0x1FFF 0000. The bootloader is designed to run from this memory area,
but both the ISP and IAP software use parts of the on-chip RAM. The RAM usage is
described later in this chapter. The interrupt vectors residing in the boot block of the
on-chip flash memory also become active after reset, i.e., the bottom 512 bytes of the
boot block are also visible in the memory region starting from the address 0x0000 0000.
Criterion for valid user code: The reserved Cortex-M0 exception vector location 7 (offset
0x 0000 001C in the vector table) should contain the 2’s complement of the check-sum of
table entries 0 through 6. This causes the checksum of the first 8 table entries to be 0. The
bootloader code checksums the first 8 locations in sector 0 of the flash. If the result is 0,
then execution control is transferred to the user code.
If the signature is not valid, the auto-baud routine synchronizes with the host via serial port
0. The host should send a ’?’ (0x3F) as a synchronization character and wait for a
response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity.
The auto-baud routine measures the bit time of the received synchronization character in
terms of its own frequency and programs the baud rate generator of the serial port. It also
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If PIO0_3 is LOW, the bootloader configures the C_CAN interface and calls the
C_CAN ISP command handler.
PIO0_3 is HIGH, the bootloader configures the UART serial port and calls the UART
ISP command handler (this is the default).
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 26: LPC111x/LPC11Cxx Flash programming firmware
Section
26.3.8.1).
UM10398
© NXP B.V. 2012. All rights reserved.
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