LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 482

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.5.3.2 Operation
28.5.5.3.3 Restrictions
28.5.5.3.4 Condition flags
28.5.5.3.5 Examples
28.5.5.4 CMP and CMN
LSRS {Rd,} Rm, Rs
LSRS {Rd,} Rm, #imm
RORS {Rd,} Rm, Rs
where:
The range of shift length depends on the instruction:
ASR — shift length from 1 to 32
LSL — shift length from 0 to 31
LSR — shift length from 1 to 32.
Remark: MOVS Rd, Rm is a pseudonym for LSLS Rd, Rm, #0.
ASR, LSL, LSR, and ROR perform an arithmetic-shift-left, logical-shift-left,
logical-shift-right or a right-rotation of the bits in the register Rm by the number of places
specified by the immediate imm or the value in the least-significant byte of the register
specified by Rs.
For details on what result is generated by the different instructions, see
Section
In these instructions, Rd, Rm, and Rs must only specify R0-R7. For non-immediate
instructions, Rd and Rm must specify the same register.
These instructions update the N and Z flags according to the result.
The C flag is updated to the last bit shifted out, except when the shift length is 0, see
Section
Compare and Compare Negative.
Rd is the destination register. If Rd is omitted, it is assumed to take the same value as
Rm.
Rm is the register holding the value to be shifted.
Rs is the register holding the shift length to apply to the value in Rm.
imm is the shift length.
ASRS R7, R5, #9 ; Arithmetic shift right by 9 bits
LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update
LSRS R4, R5, #6 ; Logical shift right by 6 bits
RORS R4, R4, R6 ; Rotate right by the value in the bottom byte of R6.
28–28.5.3.3.
28–28.5.3.3. The V flag is left unmodified.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
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Rev. 12 — 24 September 2012
UM10398
© NXP B.V. 2012. All rights reserved.
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