LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 519

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 211: SPI/SSP Status Register (SSP0SR - address
Table 212: SPI/SSP Clock Prescale Register (SSP0CPSR -
Table 213: SPI/SSP Interrupt Mask Set/Clear register
Table 214: SPI/SSP Raw Interrupt Status register (SSP0RIS
Table 215: SPI/SSP Masked Interrupt Status register
Table 216: SPI/SSP interrupt Clear Register (SSP0ICR -
Table 217. I
Table 218. Register overview: I
Table 219. I
Table 220. I
Table 221. I
Table 222. I
Table 223. I
Table 224. I
Table 225. SCLL + SCLH values for selected I
Table 226. I
Table 227. I
Table 228. I
Table 229. I
Table 230. I
Table 231. I2C0CONSET and I2C1CONSET used to
Table 232. I2C0CONSET and I2C1CONSET used to
Table 233. Abbreviations used to describe an I
Table 234. I2C0CONSET used to initialize Master
Table 235. Master Transmitter mode. . . . . . . . . . . . . . . .252
Table 236. Master Receiver mode. . . . . . . . . . . . . . . . . .255
Table 237. I2C0ADR and I2C1ADR usage in Slave Receiver
UM10398
User manual
0x4004 0008, SSP1DR - address 0x4005 8008)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .221
0x4004 000C, SSP1SR - address 0x4005 800C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .222
address 0x4004 0010, SSP1CPSR - address
0x4005 8010) bit description . . . . . . . . . . . . .222
(SSP0IMSC - address 0x4004 0014, SSP1IMSC -
address 0x4005 8014) bit description. . . . . . .223
- address 0x4004 0018, SSP1RIS - address
0x4005 8018) bit description . . . . . . . . . . . . .223
(SSP0MIS - address 0x4004 001C, SSP1MIS -
address 0x4005 801C) bit description . . . . . .224
address 0x4004 0020, SSP1ICR - address
0x4005 8020) bit description . . . . . . . . . . . . .224
0000)
0x4000 0000) bit description . . . . . . . . . . . . .235
description . . . . . . . . . . . . . . . . . . . . . . . . . . .237
description . . . . . . . . . . . . . . . . . . . . . . . . . . .237
0x4000 000C) bit description . . . . . . . . . . . . .238
address 0x4000 0010) bit description. . . . . . .238
0x4000 0014) bit description . . . . . . . . . . . . .238
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
0x4000 0018) bit description . . . . . . . . . . . . .239
- 0x4000 001C) bit description . . . . . . . . . . . .240
0x4000 00[20, 24, 28]) bit description . . . . . .241
0x4000 002C) bit description . . . . . . . . . . . . .242
0x4000 00[30, 34, 38, 3C]) bit description . . .242
configure Master mode . . . . . . . . . . . . . . . . . .243
configure Slave mode . . . . . . . . . . . . . . . . . . .244
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Transmitter mode . . . . . . . . . . . . . . . . . . . . . .250
2
2
2
2
2
2
2
2
2
2
2
2
C-bus pin description. . . . . . . . . . . . . . . . . .234
C Control Set register (I2C0CONSET - address
C Status register (I2C0STAT - 0x4000 0004) bit
C Data register (I2C0DAT - 0x4000 0008) bit
C Slave Address register 0 (I2C0ADR0-
C SCL HIGH Duty Cycle register (I2C0SCLH -
C SCL Low duty cycle register (I2C0SCLL -
C Control Clear register (I2C0CONCLR -
C Monitor mode control register (I2C0MMCTRL
C Slave Address registers (I2C0ADR[1, 2, 3]-
C Data buffer register (I2C0DATA_BUFFER -
C Mask registers (I2C0MASK[0, 1, 2, 3] -
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
2
C (base address 0x4000
All information provided in this document is subject to legal disclaimers.
2
2
C clock
C
Rev. 12 — 24 September 2012
Table 238. I2C0CONSET and I2C1CONSET used to
Table 239. Slave Receiver mode . . . . . . . . . . . . . . . . . 258
Table 240. Slave Transmitter mode . . . . . . . . . . . . . . . . 262
Table 241. Miscellaneous States . . . . . . . . . . . . . . . . . . 264
Table 242. CAN pin description (LPC11C12/C14) . . . . . 277
Table 243. CAN pin description (LPC11C22/C24) . . . . . 277
Table 244. Register overview: CCAN (base address 0x4005
Table 245. CAN control registers (CANCNTL, address
Table 246. CAN status register (CANSTAT, address
Table 247. CAN error counter (CANEC, address
Table 248. CAN bit timing register (CANBT, address
Table 249. CAN interrupt register (CANINT, address
Table 250. CAN test register (CANTEST, address
Table 251. CAN baud rate prescaler extension register
Table 252. Message interface registers . . . . . . . . . . . . . 286
Table 253. Structure of a message object in the message
Table 254. CAN message interface command request
Table 255. CAN message interface command mask
Table 256. CAN message interface command mask
Table 257. CAN message interface command mask 1
Table 258. CAN message interface command mask 2
Table 259. CAN message interface command arbitration 1
Table 260. CAN message interface command arbitration 2
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
initialize Slave Receiver mode . . . . . . . . . . . . 257
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
0x4005 0000) bit description
0x4005 0004) bit description
0x4005 0008) bit description . . . . . . . . . . . . 282
0x4005 000C) bit description . . . . . . . . . . . . . 283
0x4005 0010) bit description . . . . . . . . . . . . . 284
0x4005 0014) bit description . . . . . . . . . . . . . 284
(CANBRPE, address 0x4005 0018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
registers (CANIF1_CMDREQ, address
0x4005 0020 and CANIF2_CMDREQ, address
0x4005 0080) bit description . . . . . . . . . . . . . 287
registers (CANIF1_CMDMSK, address
0x4005 0024 and CANIF2_CMDMSK, address
0x4005 0084) bit description - write direction 287
registers (CANIF1_CMDMSK, address
0x4005 0024 and CANIF2_CMDMSK, address
0x4005 0084) bit description - read direction 288
registers (CANIF1_MSK1, address 0x4005 0028
and CANIF2_MASK1, address 0x4005 0088) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
registers (CANIF1_MSK2, address 0x4005 002C
and CANIF2_MASK2, address 0x4005 008C) bit
description
registers (CANIF1_ARB1, address 0x4005 0030
and CANIF2_ARB1, address 0x4005 0090) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
registers (CANIF1_ARB2, address 0x4005 0034
and CANIF2_ARB2, address 0x4005 0094) bit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Chapter 29: Supplementary information
UM10398
© NXP B.V. 2012. All rights reserved.
519 of 538