LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 467

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.3.1 Operands
28.5.3.2 Restrictions when using PC or SP
28.5.3 About the instruction descriptions
Table 430. CMSIS intrinsic functions to generate some Cortex-M0 instructions
The CMSIS also provides a number of functions for accessing the special registers using
MRS and MSR instructions:
Table 431. CMSIS intrinsic functions to access the special registers
The following sections give more information about using the instructions:
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination
register. When there is a destination register in the instruction, it is usually specified before
the other operands.
Many instructions are unable to use, or have restrictions on whether you can use, the
Program Counter (PC) or Stack Pointer (SP) for the operands or destination register.
See instruction descriptions for more information.
Instruction
REV
REV16
REVSH
SEV
WFE
WFI
Special register
PRIMASK
CONTROL
MSP
PSP
•
•
•
•
•
•
Section 28.5.3.1 “Operands”
Section 28.5.3.2 “Restrictions when using PC or SP”
Section 28.5.3.3 “Shift Operations”
Section 28.5.3.4 “Address alignment”
Section 28.5.3.5 “PC-relative expressions”
Section 28.5.3.6 “Conditional
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Access
Read
Write
Read
Write
Read
Write
Read
Write
execution”.
CMSIS function
uint32_t __get_PRIMASK (void)
void __set_PRIMASK (uint32_t value)
uint32_t __get_CONTROL (void)
void __set_CONTROL (uint32_t value)
uint32_t __get_MSP (void)
void __set_MSP (uint32_t TopOfMainStack)
uint32_t __get_PSP (void)
void __set_PSP (uint32_t TopOfProcStack)
CMSIS intrinsic function
uint32_t __REV(uint32_t int value)
uint32_t __REV16(uint32_t int value)
uint32_t __REVSH(uint32_t int value)
void __SEV(void)
void __WFE(void)
void __WFI(void)
UM10398
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