LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 38

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.5.33 Deep-sleep mode configuration register
This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit
when the device enters Deep-sleep mode.
This register must be initialized at least once before entering Deep-sleep mode with
one of the four values shown in
Table 40.
Remark: Failure to initialize and program this register correctly may result in undefined
behavior of the microcontroller. The values listed in
for PDSLEEPCFG register.
To select the appropriate power configuration for Deep-sleep mode, consider the
following:
Remark: Reserved bits in this register must always be written as indicated. This register
must be initialized correctly before entering Deep-sleep mode.
Table 41.
Configuration
BOD on
BOD off
Bit
2:0
3
5:4
6
7
•
•
BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event
occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an
additional current drain in Deep-sleep mode.
WD oscillator: The watchdog oscillator can be left running in Deep-sleep mode to
provide a clock for the watchdog timer or a general purpose timer if they are needed
for timing a wake-up event (see
oscillator analog output frequency must be set to its lowest value (bits FREQSEL in
the WDTOSCCTRL = 0001, see
timer clock must be disabled in the SYSAHBCLKCTRL register (see
entering Deep-sleep mode.
The watchdog oscillator, if running, contributes an additional current drain in
Deep-sleep mode.
Symbol
NOTUSED
BOD_PD
NOTUSED
WDTOSC_PD
NOTUSED
Allowed values for PDSLEEPCFG register
Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit
description
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
Value
0
1
0
1
WD oscillator on
PDSLEEPCFG = 0x0000 18B7 PDSLEEPCFG = 0x0000 18F7
PDSLEEPCFG = 0x0000 18BF PDSLEEPCFG = 0x0000 18FF
Table
Description
Reserved. Always write these bits as 111.
BOD power-down control in Deep-sleep mode, see
Table
Powered
Powered down
Reserved. Always write these bits as 11.
Watchdog oscillator power control in Deep-sleep
mode, see
Powered
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Reserved. Always write this bit as 1.
Section 3.10.3
Table
40:
40.
13) and all peripheral clocks other than the
Table
40.
for details). In this case, the watchdog
Table 40
WD oscillator off
are the only values allowed
UM10398
© NXP B.V. 2012. All rights reserved.
Table
21) before
38 of 538
Reset
value
0
0
0
0
0