LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 302

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
Fig 64. Block diagram of a message object transfer
APB
bus
16.7.3.1 Management of message objects
IF1 COMMAND REQUEST
IF2 COMMAND REQUEST
COMMAND REGISTERS
IF1 COMMAND MASK
IF2 COMMAND MASK
IF1 ARBITRATION 1/2
MESSAGE BUFFER
IF2 ARBITRATION 1/2
IF1 MESSAGE CTRL
IF2 MESSAGE CTRL
IF1 DATA A1/2
IF1 DATA B1/2
IF1 MASK1, 2
IF2 DATA A1/2
IF2 DATA B1/2
REGISTERS
IF2 MASK1, 2
INTERFACE
The configuration of the Message Objects in the Message RAM will (with the exception of
the bits MSGVAL, NEWDAT, INTPND, and TXRQST) is not be affected by resetting the
chip. All the Message Objects must be initialized by the CPU or they must be set to not
valid (MSGVAL = ‘0’).The bit timing must be configured before the CPU clears the INIT bit
in the CAN Control Register.
The configuration of a Message Object is done by programming Mask, Arbitration, Control
and Data field of one of the two interface register sets to the desired values. By writing to
the corresponding IFx Command Request Register, the IFx Message Buffer Registers are
loaded into the addressed Message Object in the Message RAM.
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•
•
•
•
•
Data Transfer from Shift Register to the Message RAM
Data Transfer from Message RAM to Shift Register
Data Transfer from Shift Register to the Acceptance Filtering unit
Scanning of Message RAM for a matching Message Object
Handling of TXRQST flags
Handling of interrupts
message object
All information provided in this document is subject to legal disclaimers.
read transfer
transfer a
write transfer
Rev. 12 — 24 September 2012
TRANSMISSION REQUEST 1/2
INTERRUPT PENDING1/2
MESSAGE OBJECT 32
MESSAGE OBJECT 1
MESSAGE OBJECT 2
MESSAGE HANDLER
MESSAGE VALID1/2
MESSAGE RAM
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
NEW DATA 1/2
.
.
.
SHIFT REGISTERS
CAN CORE/
UM10398
© NXP B.V. 2012. All rights reserved.
CAN frame
transfer a
receive
transmit
302 of 538
CAN
bus