LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 47

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.9.4.1 Power configuration in Deep power-down mode
3.9.4.2 Programming Deep power-down mode
3.9.4.3 Wake-up from Deep power-down mode
All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin.
Deep power-down mode has no configuration options. All clocks, the core, and all
peripherals are powered down. Only the WAKEUP pin is powered.
The following steps must be performed to enter Deep power-down mode:
Remark: The WAKEUP pin must be pulled HIGH externally before entering Deep
power-down mode.
Pulling the WAKEUP pin LOW wakes up the LPC111x/LPC11Cxx from Deep power-down,
and the chip goes through the entire reset process
width for the HIGH-to-LOW transition on the WAKEUP pin is 50 ns.
Follow these steps to wake up the chip from Deep power-down mode:
Remark: The RESET pin has no functionality in Deep power-down mode.
1. Write one to the DPDEN bit in the PCON register (see
2. Store data to be retained in the general purpose registers
3. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register
4. Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in
5. Use the ARM WFI instruction.
1. A wake-up signal is generated when a HIGH-to-LOW transition occurs externally on
2. Once the chip has booted, read the deep power-down flag in the PCON register
3. Clear the deep power-down flag in the PCON register
4. (Optional) Read the stored data in the general purpose registers
5. Set up the PMU for the next Deep power-down cycle.
the PDRUNCFG register before entering Deep power-down mode.
Remark: This step is part dependent.
the WAKEUP pin with a pulse length of at least 50 ns while the part is in Deep
power-down mode.
– The PMU will turn on the on-chip voltage regulator. When the core voltage reaches
– All registers except the GPREG0 to GPREG4and PCON will be in their reset state.
(Table
power-down.
Table
the power-on-reset (POR) trip point, a system reset will be triggered and the chip
re-boots.
51).
49) to verify that the reset was caused by a wake-up event from Deep
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
See
Section 3.1
(Section
(Table
for part specific details.
Table
3.6). The minimum pulse
(Table
49).
49).
50).
(Table 50
UM10398
© NXP B.V. 2012. All rights reserved.
(Table
and
452).
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