LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 238

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
15.7.5.1 Selecting the appropriate I
15.7.5 I
Table 222. I
and I2C0SCLL- 0x4000 0014)
Table 223. I
Table 224. I
Software must set values for the registers SCLH and SCLL to select the appropriate data
rate and duty cycle. SCLH defines the number of I2C_PCLK cycles for the SCL HIGH
time, SCLL defines the number of I2C_PCLK cycles for the SCL low time. The frequency
is determined by the following formula (I2C_PCLK is the frequency of the peripheral I2C
clock):
The values for SCLL and SCLH must ensure that the data rate is in the appropriate I
data rate range. Each register value must be greater than or equal to 4.
some examples of I
values.
Table 225. SCLL + SCLH values for selected I
Bit
0
7:1
31:8 -
Bit
15:0
31:16
Bit
15:0
31:16
I
Standard mode
Fast-mode
Fast-mode Plus
2
2
C SCL HIGH and LOW duty cycle registers (I2C0SCLH - 0x4000 0010
C mode
Symbol Description
GC
Address The I
Symbol
SCLH
-
Symbol
SCLL
-
description
2
2
2
C Slave Address register 0 (I2C0ADR0- 0x4000 000C) bit description
C SCL HIGH Duty Cycle register (I2C0SCLH - address 0x4000 0010) bit
C SCL Low duty cycle register (I2C0SCLL - 0x4000 0014) bit description
General Call enable bit.
Reserved. The value read from a reserved bit is not defined.
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I
frequency
100 kHz
400 kHz
1 MHz
Description
Count for SCL HIGH time period selection.
Reserved. The value read from a reserved bit is not defined.
Description
Count for SCL low time period selection.
Reserved. The value read from a reserved bit is not defined.
2
C bit
2
2
C-bus rates based on I2C_PCLK frequency and SCLL and SCLH
Rev. 12 — 24 September 2012
C device address for slave mode.
I 2 C
6
60
15
-
2
C data rate and duty cycle
bitfrequency
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
8
80
20
8
10
100
25
10
=
2
C clock values
------------------------------------
SCLH
I2CPCLK
12
120
30
12
I2C_PCLK (MHz)
SCLH + SCLL
+
SCLL
16
160
40
16
20
200
50
20
30
300
75
30
UM10398
© NXP B.V. 2012. All rights reserved.
Table 225
Reset value
0
0x00
-
Reset value
0x0004
-
Reset value
0x0004
-
40
400
100
40
238 of 538
gives
50
500
125
50
2
C
(4)