LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 22

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 7.
UM10398
User manual
Name
SYSOSCCTRL
WDTOSCCTRL
IRCCTRL
-
SYSRSTSTAT
-
SYSPLLCLKSEL
SYSPLLCLKUEN
-
MAINCLKSEL
MAINCLKUEN
SYSAHBCLKDIV
-
SYSAHBCLKCTRL
-
SSP0CLKDIV
UARTCLKDIV
SSP1CLKDIV
-
WDTCLKSEL
WDTCLKUEN
WDTCLKDIV
-
CLKOUTCLKSEL
CLKOUTUEN
CLKOUTCLKDIV
-
PIOPORCAP0
PIOPORCAP1
-
BODCTRL
SYSTCKCAL
-
NMISRC
-
STARTAPRP0
STARTERP0
STARTRSRP0CLR
STARTSRP0
Register overview: system control block (base address 0x4004 8000)
Access
R/W
R/W
R/W
-
R/W
-
R/W
R/W
-
R/W
R/W
R/W
-
R/W
-
R/W
R/W
R/W
-
R/W
R/W
R/W
-
R/W
R/W
R/W
-
R
R
R
R/W
R/W
-
R/W
-
R/W
R/W
W
R
Address offset Description
0x020
0x024
0x028
0x02C
0x030
0x034 - 0x03C
0x040
0x044
0x048 - 0x06C
0x070
0x074
0x078
0x07C
0x080
0x084 - 0x090
0x094
0x098
0x09C
0x0A0-0x0CC
0x0D0
0x0D4
0x0D8
0x0DC
0x0E0
0x0E4
0x0E8
0x0EC - 0x0FC Reserved
0x100
0x104
0x108 - 0x14C
0x150
0x154
0x158 - 0x170
0x174
0x178 - 0x1FC
0x200
0x204
0x208
0x20C
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
System oscillator control
Watchdog oscillator control
IRC control
Reserved
System reset status register
Reserved
System PLL clock source select
System PLL clock source update enable
Reserved
Main clock source update enable
System AHB clock divider
Reserved
Reserved
SPI0 clock divider
UART clock divder
SPI1 clock divder
Reserved
WDT clock source select
WDT clock source update enable
WDT clock divider
Reserved
CLKOUT clock source select
CLKOUT clock source update enable
CLKOUT clock divider
POR captured PIO status 0
POR captured PIO status 1
Reserved
BOD control
System tick counter calibration
Reserved
NMI source selection
Reserved
Start logic edge control register 0
Start logic signal enable register 0
Start logic status register 0
Main clock source select
System AHB clock control
Start logic reset register 0
…continued
Reset
value
0x000
0x000
0x080
-
0x000
-
0x000
0x000
-
0x000
0x000
0x001
-
0x85F
-
0x000
0x000
0x000
-
0x000
0x000
0x000
-
0x000
0x000
0x000
-
user
dependent
user
dependent
-
0x000
0x004
-
0x000
-
n/a
n/a
UM10398
© NXP B.V. 2012. All rights reserved.
Reference
Table 12
Table 13
Table 14
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Table 15
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Table 16
Table 17
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Table 18
Table 19
Table 20
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Table 21
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Table 22
Table 23
Table 24
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Table 26
Table 27
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Table 28
Table 29
Table 30
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Table 31
Table 32
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Table 33
Table 34
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Table 35
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Table 36
Table 37
Table 38
Table 39
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