LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 229

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
14.7.2.5 SPI format with CPOL = 1,CPHA = 1
14.7.3 Semiconductor Microwire frame format
The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in
Figure
In this configuration, during idle periods:
If the SPI/SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. Master’s MOSI is
enabled. After a further one half SCK period, both master and slave data are enabled onto
their respective transmission lines. At the same time, the SCK is enabled with a falling
edge transition. Data is then captured on the rising edges and propagated on the falling
edges of the SCK signal.
After all bits have been transferred, in the case of a single word transmission, the SSEL
line is returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transmissions, the SSEL pins remains in its active LOW
state, until the final bit of the last word has been captured, and then returns to its idle state
as described above. In general, for continuous back-to-back transfers the SSEL pin is
held LOW between successive data words and termination is the same as that of the
single word transfer.
Figure 41
format when back-to-back frames are transmitted.
Fig 40. SPI Frame Format with CPOL = 1 and CPHA = 1
•
•
•
The CLK signal is forced HIGH.
SSEL is forced HIGH.
The transmit MOSI/MISO pad is in high impedance.
40, which covers both single and continuous transfers.
shows the Microwire frame format for a single frame.
All information provided in this document is subject to legal disclaimers.
SSEL
MOSI
MISO
SCK
Rev. 12 — 24 September 2012
Q
MSB
MSB
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
4 to 16 bits
LSB
LSB
Figure 42
Q
UM10398
© NXP B.V. 2012. All rights reserved.
shows the same
229 of 538