LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 526

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
29.6 Contents
Chapter 1: LPC111x/LPC11Cxx Introductory information
1.1
1.2
1.3
Chapter 2: LPC111x/LPC11Cxx Memory mapping
2.1
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.5.10
3.5.11
3.5.12
3.5.13
3.5.14
3.5.15
3.5.16
3.5.17
3.5.18
3.5.19
3.5.20
3.5.21
3.5.22
3.5.23
3.5.24
3.5.25
3.5.26
3.5.27
3.5.28
3.5.29
3.5.30
3.5.31
3.5.32
UM10398
User manual
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering information . . . . . . . . . . . . . . . . . . . . . 7
How to read this chapter . . . . . . . . . . . . . . . . . 16
How to read this chapter . . . . . . . . . . . . . . . . . 19
General description . . . . . . . . . . . . . . . . . . . . . 19
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock generation . . . . . . . . . . . . . . . . . . . . . . . 20
Register description . . . . . . . . . . . . . . . . . . . . 21
DEVICE_ID register . . . . . . . . . . . . . . . . . . . . .19
C_CAN controller . . . . . . . . . . . . . . . . . . . . . . .19
Entering Deep power-down mode . . . . . . . . . .19
Enabling sequence for UART clock . . . . . . . . .19
NMI source selection register . . . . . . . . . . . . . .19
System memory remap register . . . . . . . . . . . 23
Peripheral reset control register . . . . . . . . . . . 23
System PLL control register . . . . . . . . . . . . . . 24
System PLL status register. . . . . . . . . . . . . . . 24
System oscillator control register . . . . . . . . . . 25
Watchdog oscillator control register . . . . . . . . 25
Internal resonant crystal control register. . . . . 26
System reset status register . . . . . . . . . . . . . . 26
System PLL clock source select register . . . . 27
System PLL clock source update enable
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Main clock source select register . . . . . . . . . . 28
Main clock source update enable register . . . 28
System AHB clock divider register . . . . . . . . . 29
System AHB clock control register . . . . . . . . . 29
SPI0 clock divider register . . . . . . . . . . . . . . . 31
UART clock divider register . . . . . . . . . . . . . . 31
SPI1 clock divider register . . . . . . . . . . . . . . . 31
WDT clock source select register . . . . . . . . . . 32
WDT clock source update enable register . . . 32
WDT clock divider register . . . . . . . . . . . . . . . 32
CLKOUT clock source select register. . . . . . . 33
CLKOUT clock source update enable register 33
CLKOUT clock divider register . . . . . . . . . . . . 34
POR captured PIO status register 0 . . . . . . . . 34
POR captured PIO status register 1 . . . . . . . . 34
BOD control register . . . . . . . . . . . . . . . . . . . . 35
System tick counter calibration register . . . . . 35
NMI source selection register . . . . . . . . . . . . . 35
Start logic edge control register 0 . . . . . . . . . . 36
Start logic signal enable register 0 . . . . . . . . . 36
Start logic reset register 0 . . . . . . . . . . . . . . . . 37
Start logic status register 0 . . . . . . . . . . . . . . 37
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
1.4
1.5
2.2
3.5.33
3.5.34
3.5.35
3.5.36
3.6
3.7
3.8
3.9
3.9.1
3.9.1.1
3.9.2
3.9.2.1
3.9.2.2
3.9.2.3
3.9.3
3.9.3.1
3.9.3.2
3.9.3.3
3.9.4
3.9.4.1
3.9.4.2
3.9.4.3
3.10
3.10.1
3.10.2
3.10.3
3.11
3.11.1
3.11.2
3.11.3
3.11.4
3.11.4.1
3.11.4.2
3.12
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ARM Cortex-M0 processor . . . . . . . . . . . . . . . 15
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Start-up behavior. . . . . . . . . . . . . . . . . . . . . . . 43
Brown-out detection . . . . . . . . . . . . . . . . . . . . 43
Power management . . . . . . . . . . . . . . . . . . . . 44
Deep-sleep mode details . . . . . . . . . . . . . . . . 48
System PLL functional description . . . . . . . . 49
Flash memory access. . . . . . . . . . . . . . . . . . . 51
Deep-sleep mode configuration register . . . . 38
Wake-up configuration register . . . . . . . . . . . 39
Power-down configuration register . . . . . . . . 40
Device ID register . . . . . . . . . . . . . . . . . . . . . 41
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power configuration in Active mode. . . . . . . . 44
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power configuration in Sleep mode . . . . . . . . 44
Programming Sleep mode . . . . . . . . . . . . . . . 45
Wake-up from Sleep mode . . . . . . . . . . . . . . 45
Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 45
Power configuration in Deep-sleep mode . . . 45
Programming Deep-sleep mode . . . . . . . . . . 45
Wake-up from Deep-sleep mode . . . . . . . . . . 46
Deep power-down mode . . . . . . . . . . . . . . . . 46
Power configuration in Deep power-down mode .
47
Programming Deep power-down mode . . . . . 47
Wake-up from Deep power-down mode . . . . 47
IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 48
Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Using the general purpose counter/timers to
create a self-wake-up event. . . . . . . . . . . . . . 48
Lock detector . . . . . . . . . . . . . . . . . . . . . . . . . 49
Power-down control . . . . . . . . . . . . . . . . . . . . 50
Divider ratio programming . . . . . . . . . . . . . . . 50
Post divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Feedback divider . . . . . . . . . . . . . . . . . . . . . . . 50
Changing the divider values. . . . . . . . . . . . . . . 50
Frequency selection. . . . . . . . . . . . . . . . . . . . 50
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 51
Power-down mode . . . . . . . . . . . . . . . . . . . . . 51
Chapter 29: Supplementary information
UM10398
© NXP B.V. 2012. All rights reserved.
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