LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 379

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
21.7.12 PWM Control Register (TMR32B0PWMC and TMR32B1PWMC)
Table 340: Count Control Register (TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For each timer, a maximum of three-single edge controlled PWM outputs can be selected
on the MATn[2:0] outputs. One additional match register determines the PWM cycle
length. When a match occurs in any of the other match registers, the PWM output is set to
HIGH. The timer is reset by the match register that is configured to set the PWM cycle
length. When the timer is reset to zero, all currently HIGH match outputs configured as
PWM outputs are cleared.
Table 341: PWM Control Register (TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC -
Bit
7:5
31:8
Bit
0
1
2
Symbol
SELCC
-
Symbol
PWMEN0
PWMEN1
PWMEN2
- address 0x4001 8070) bit description
0x4001 8074) bit description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
-
Value
0
1
0
1
0
1
Rev. 12 — 24 September 2012
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
Description
When bit 4 is one, these bits select which capture input edge
will cause the timer and prescaler to be cleared. These bits
have no effect when bit 4 is zero.
Rising Edge of CAP0 clears the timer (if bit 4 is set).
Falling Edge of CAP0 clears the timer (if bit 4 is set).
Rising Edge of CAP1 clears the timer (if bit 4 is set).
Falling Edge of CAP1 clears the timer (if bit 4 is set).
Reserved.
Reserved.
Reserved.
Reserved.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
PWM channel 0 enable
CT32Bn_MAT0 is controlled by EM0.
PWM mode is enabled for CT32Bn_MAT0.
PWM channel 1 enable
CT32Bn_MAT1 is controlled by EM1.
PWM mode is enabled for CT32Bn_MAT1.
PWM channel 2 enable
CT32Bn_MAT2 is controlled by EM2.
PWM mode is enabled for CT32Bn_MAT2.
…continued
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
0
0
0
379 of 538
Reset
value
0
-