LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 385

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
22.6 Clock control
UM10398
User manual
Fig 84. Windowed Watchdog Timer (WWDT) block diagram
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers and is derived from the system clock (see
The WDCLK is used for the watchdog timer counting and is derived from the WDT clock
divider in
IRC, the watchdog oscillator, and the main clock. The clock source is selected in the
syscon block (see
also disable this clock.
There is some synchronization logic between these two clock domains. When the
WDMOD and WDTC registers are updated by APB operations, the new value will take
effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog
timer is counting on WDCLK, the synchronization logic will first lock the value of the
counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV
register by the CPU.
The watchdog oscillator can be powered down in the PDRUNCFG register
is not used. The clock to the watchdog register block (PCLK) can be disabled in the
SYSAHBCLKCTRL register
Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register (see
Table
wd_clk
MOD
register
13) before using the watchdog oscillator for the WDT.
Figure
feed sequence
detect and
FEED
protection
WDPROTECT
(MOD
All information provided in this document is subject to legal disclaimers.
8. Several clocks can be used as a clock source for wdt_clk clock: the
Chapter 22: LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT)
[ 4])
Table
feed error
÷4
Rev. 12 — 24 September 2012
range
( MOD
in
WDTOF
25). The WDCLK has its own clock divider
feed ok
WINDOW
compare
compare
underflow
[2])
0
(Table
24-bit down counter
(MOD
WDINT
TC
interrupt
compare
WDTV
21) for power savings.
WDINTVAL
[3])
compare
WDRESET
(MOD
enable count
[1])
feed ok
(MOD
shadow bit
WDEN
[0])
chip reset
watchdog
interrupt
(Table
UM10398
© NXP B.V. 2012. All rights reserved.
27) which can
(Table
Figure
385 of 538
43) if it
8).