LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 383

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

22.1 How to read this chapter
22.2 Basic configuration
22.3 Features
UM10398
User manual
This chapter describes the Windowed WDT available on all parts of the LPC1100L and
:LPC1100XL series.
The WDT is configured using the following registers:
1. Pins: The WDT uses no external pins.
2. Power: In the SYSAHBCLKCTRL register, set bit 15
3. Peripheral clock: Select the WDT clock source
4. Lock features: Once the watchdog timer is enabled by setting the WDEN bit in the
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UM10398
Chapter 22: LPC111x/LPC11Cxx Windowed WatchDog Timer
(WDT)
Rev. 12 — 24 September 2012
peripheral clock by writing to the WDTCLKDIV register
Remark: The frequency of the watchdog oscillator is undefined after reset. The
watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL
register (see
WDMOD register, the following lock features are in effect:
a. The WDEN bit cannot be changed to 0, that is the WDT cannot be disabled.
b. The watch dog clock source cannot be changed. If the WDT is needed in
Internally resets chip if not reloaded during the programmable time-out period.
Optional windowed operation requires reload to occur between a minimum and
maximum time-out period, both programmable.
Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
Programmable 24-bit timer with internal fixed pre-scaler.
Selectable time period from 1,024 watchdog clocks (T
million watchdog clocks (T
“Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog
reset to be disabled.
A dedicated on-chip watchdog oscillator provides a reliable clock source that cannot
be turned off when the Watchdog Timer is running.
Incorrect feed sequence causes immediate watchdog reset if the watchdog is
enabled.
The watchdog reload value can optionally be protected such that it can only be
changed after the “warning interrupt” time is reached.
Deep-sleep mode, select the watch dog oscillator as the clock source before
setting the WDEN bit.
All information provided in this document is subject to legal disclaimers.
Table
Rev. 12 — 24 September 2012
13) before using the watchdog oscillator for the WDT.
WDCLK
 2
24
 4) in increments of 4 watchdog clocks.
(Table
(Table
25) and enable the WDT
WDCLK
(Table
21).
 256  4) to over 67
27).
© NXP B.V. 2012. All rights reserved.
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